7 nm process
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET technology, a type of multi-gate MOSFET technology.
Taiwan Semiconductor Manufacturing Company began production of 256 Mbit SRAM memory chips using a 7 nm process in 2017, before Samsung began mass production of 7 nm devices in 2018. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC.
AMD has released their "Rome" processors for servers and datacenters, which are based on TSMC's 7nm node and feature up to 64 cores and 128 threads. They have also released their "Matisse" consumer desktop processors with 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module is fabricated with the 14 nm process, while the Matisse's I/O die uses the TSMC 12 nm process. The Radeon RX 5000 series is also based on the 7 nm process.
History
Technology demos
7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Turkish engineer Omer Dokumaci, Taiwanese engineer Meikei Ieong and Romanian engineer Anda Mocuta fabricated a 6 nm silicon-on-insulator MOSFET. In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.
In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process, with a cell area of 0.027 mm2 with reasonable risk production yields.
Expected commercialization and technologies
In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017. In April 2017, TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm process, with extreme ultraviolet lithography. TSMC's 7 nm production plans, as of early 2017, were to use deep ultraviolet immersion lithography initially on this process node, and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.
In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process. The company has not published any expected values for feature lengths at this process node.
In April 2018, TSMC announced volume production of 7 nm chips. In June 2018, the company announced mass production ramp up.
In May 2018, Samsung announced production of 7 nm chips this year. ASML Holding NV is their main supplier of EUV lithography machines.
In June 2018, AMD announced 7 nm Radeon Instinct GPUs launching in the second half of 2018. In August 2018, the company confirmed the release of the GPUs.
In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips, citing cost.
On August 21, 2018, Huawei announced their HiSilicon Kirin 980 SoC to be used in their Huawei Mate 20 and Mate 20 Pro built using TSMC's 7 nm process.
On September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20. In October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm process.
On October 28, 2018, Samsung announced their second generation 7 nm process had entered risk production and should enter mass production in 2019.
On December 4, 2018, Qualcomm announced their Snapdragon 855 and 8cx built using TSMC's 7 nm process. The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.
On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers will have "different flavors" of second generation 7 nm.
On April 16, 2019, TSMC announced their 6 nm process called, which is expected to be in mass products from 2021. N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.
On July 28, 2019, TSMC announced their second gen 7 nm process called N7P, which is DUV-based like their N7 process. Since N7P is fully IP-compatible with the original 7 nm, while N7+ is not, N7+ is a separate process from '7 nm'. N6, another EUV-based process, is planned to be released later than even TSMC's 5 nm process, with the IP-compatibility with N7. At their Q1 2019 earnings call, TSMC reiterated their Q4 2018 statement that N7+ would generate less than $1 billion TWD in revenue in 2019.
On May 29, 2019, MediaTek announced their 5G SoC built using a TSMC 7 nm process.
On August 6, 2019, Samsung announced their Exynos 9825 SoC, the first chip built using their 7LPP process. The Exynos 9825 is the first mass market chip built featuring EUVL.
On September 6, 2019, Huawei announced their HiSilicon Kirin 990 4G & 990 5G SoCs, built using TSMC's N7 and N7+ processes.
On September 10, 2019, Apple announced their A13 Bionic chip used in iPhone 11 and iPhone 11 Pro built using TSMC's 2nd gen N7P process.
On October 5, 2019, AMD announced their EPYC Roadmap, featuring Milan chips built using TSMC's N7+ process.
On October 7, 2019, TSMC announced they started delivering N7+ products to market in high volume.
Technology commercialization
On July 7, 2019, AMD officially launched their Ryzen 3000 series of central processing units, based on the TSMC 7 nm process and Zen 2 microarchitecture.7 nm patterning difficulties
The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension control as well as pattern placement, all involving neighboring features.Pitch splitting
Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.Spacer patterning
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'. Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation, the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.When self-aligned quadruple patterning is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.
Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.
EUV lithography
is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus. This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures. The defect level is on the order of 1K/mm2.
The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint. A separate exposure for cutting lines is preferred.
Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength, whereas this resolution enhancement is not available for EUV.
Comparison with previous nodes
Due to these challenges, 7 nm poses unprecedented patterning difficulty in the back end of line. The previous high-volume, long-lived foundry node used pitch splitting for the tighter pitch metal layers.Cycle time: immersion vs. EUV
Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.7 nm process nodes and process offerings
The naming of process nodes by different major manufacturers is partially marketing-driven and not directly related to any measurable distance on a chip for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.Since EUV implementation at 7 nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7 nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.
| TSMC N7FF | Samsung 7LPP | Intel 10 nm | TSMC N7P | TSMC N7FF+ | TSMC N6 | |
| Transistor density | 96.5 | 95.3 81.07 85.57 | 100.76 | same as N7FF | 113.9 | 114.2 |
| SRAM bit-cell size | 0.027 μm2 | μm2 | 0.0312 μm2 | same as N7FF | ||
| Transistor Gate Pitch | 54 nm | 54 nm | 54 nm | same as N7FF | ||
| Transistor Fin Pitch | 27 nm | 34 nm | same as N7FF | |||
| Transistor Fin Height | 53 nm | |||||
| Minimum pitch | 40 nm | 46 nm | 36 nm | same as N7FF | < 40 nm | |
| EUV implementation | None, used self-aligned quad patterning instead | 36 nm pitch metal; 20% of total layer set | None. Relied on SAQP heavily | - | 4 layers | 5 layers |
| EUV-limited wafer output | N/A | 1500 wafers/day | N/A | N/A | ~ 1000 wafers/day | |
| Multipatterning | Fins Gate Contacts/vias Lowest 10 metal layers | Fins Gate Vias Metal 1 44 nm pitch metal | Same as 7FF | Same as 7FF, with reduction on 4 EUV layers | Same as 7FF, with reduction on 5 EUV layers | |
| Release status |