22 nm process


The 22 nm node is the process step following the 32 nm in MOSFET semiconductor device fabrication. The typical half-pitch for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012.
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm, which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.
The 20-nanometre node is an intermediate half-node die shrink based on the 22-nanometre process.
TSMC began mass production of 20nm nodes in 2014. The 22 nm process was superseded by commercial 14 nm FinFET technology in 2014.

Technology demos

In 1998, FinFET devices down to 17nm were demonstrated by an international team of researchers working at UC Berkeley, led by Digh Hisamoto from Japan's Hitachi Central Research Laboratory and Chenming Hu from the Taiwan Semiconductor Manufacturing Company, along with Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano, Tsu-Jae King Liu and Jeffrey Bokor. In December 2000, a 20nm FinFET process was demonstrated by the same research team.
On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2. The cell was printed using immersion lithography.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm2, smallest reported to date.
On January 3, 2010, Intel and Micron Technology announced the first in a family of 25 nm NAND devices.
On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a FinFET technology called 3-D Tri-Gate.
IBM's POWER8 processors are produced in a 22 nm SOI process.

Shipped devices