The term die shrink refers to the scaling of metal-oxide-semiconductor devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, usually involving an advance of lithographicnodes. This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.
Details
Die shrinks are the key to improving price/performance at semiconductor companies such as Samsung, Intel, TSMC, and SK Hynix, and fabless manufacturers such as AMD, NVIDIA and MediaTek. Examples in the 2000s include the downscaling of the PlayStation 2's Emotion Engine processor from Sony and Toshiba, the codenamed Cedar MillPentium 4 processors and Penryn Core 2 processors, the codenamed BrisbaneAthlon 64 X2 processors, various generations of GPUs from both ATI and NVIDIA, and various generations of RAM and flash memory chips from Samsung, Toshiba and SK Hynix. In January 2010, Intel released ClarkdaleCore i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture. Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture is followed by a die shrink to improve performance with the same microarchitecture. Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption, increased clock rate headroom, and lower prices. Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps, and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.
Half-shrink
In CPU fabrications, a die shrink always involves an advance to a lithographic node as defined by ITRS. For GPU and SoC manufacturing, the die shrink often involves shrinking the die on a node not defined by the ITRS, for instance the 150 nm, 110 nm, 80 nm, 55 nm, 40 nm and more currently 8 nm nodes, sometimes referred to as "half-nodes". This is a stopgap between two ITRS-defined lithographic nodes before further shrink to the lower ITRS-defined nodes occurs, which helps save further R&D cost. The choice to perform die shrinks to either full-nodes or half-nodes rests with the foundry and not the integrated circuit designer.
