Opteron
Opteron is AMD's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture. It was released on April 22, 2003, with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture were announced on September 10, 2007, featuring a new quad-core configuration. The most-recently released Opteron CPUs are the Piledriver-based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively. In January 2016, the first ARMv8-A based Opteron SoC was released.
Technical description
Two key capabilities
Opteron combines two important capabilities in a single processor:- native execution of legacy x86 32-bit applications without speed penalties
- native execution of x86-64 64-bit applications
The Opteron processor possesses an integrated memory controller supporting DDR SDRAM, DDR2 SDRAM or DDR3 SDRAM. This both reduces the latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip.
Multi-processor features
In multi-processor systems, the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional routing chips to support more than 8 CPUs per box.In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel Xeon which didn't have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a switched fabric, rather than a shared bus. In particular, the Opteron's integrated memory controller allows the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, contention for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for the Intel Core i7 family of processors and their Xeon derivatives.
Multi-core Opterons
In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant dual-core; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver the performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost.AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2 GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For multithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252.
Second-generation Opterons are offered in three series: the 1000 Series, the 2000 Series, and the 8000 Series. The 1000 Series uses the AM2 socket. The 2000 Series and 8000 Series use Socket F.
AMD announced its third-generation quad-core Opteron chips on September 10, 2007
with hardware vendors announcing servers in the following month. Based on a core design codenamed Barcelona, new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips.
The fourth generation was announced in June 2009 with the Istanbul hexa-cores. It introduced HT Assist, an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated.
In March 2010 AMD released the Magny-Cours Opteron 6100 series CPUs for Socket G34. These are 8- and 12-core multi-chip module CPUs consisting of two four or six-core dies with a HyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz for the Istanbul CPUs to 3.20 GHz.
AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications.
Socket 939
AMD released Socket 939 Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1 MB L2 Cache the Socket 939 Opterons are identical to the San Diego and Toledo core Athlon 64s, but are run at lower clock speeds than the cores are capable of, making them more stable.Socket AM2
Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike the majority of their Athlon 64 X2 cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224.Socket AM2+
AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to the Agena Phenom X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest." The Socket AM2+ Opterons carry model numbers of 1352, 1354, and 1356Socket AM3
AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on a 45 nm manufacturing process and are similar to the Deneb-based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka." These CPUs carry model numbers of 1381, 1385, and 1389Socket AM3+
was introduced in 2011 and is a modification of AM3 for the Bulldozer microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx.Socket F
is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. The “Lidded land grid array” socket adds support for DDR2 SDRAM and improved HyperTransport version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with socket 1207 FX.Socket G34
is one of the third generation of Opteron sockets, along with Socket C32. This socket supports Magny-Cours Opteron 6100, Bulldozer-based Interlagos Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of DDR3 SDRAM. Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to the traditional registered ECC RAM.Socket C32
is the other member of the third generation of Opteron sockets. This socket is physically similar to Socket F but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM.Micro-architecture update
The Opteron line saw an update with the implementation of the AMD K10 microarchitecture. New processors, launched in the third quarter of 2007, incorporate a variety of improvements, particularly in memory prefetching, speculative loads, SIMD execution and branch prediction, yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.In 2007 AMD introduced a scheme to characterize the power consumption of new processors under "average" daily usage, named average CPU power.
Socket FT3
The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or Socket FT3.Features
CPUs
APUs
Models
For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form Opteron XYY. For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in the form Opteron XZYY. For all first, second, and third-generation Opterons, the first digit specifies the number of CPUs on the target machine:- 1 – Designed for [|uniprocessor systems]
- 2 – Designed for [|dual-processor systems]
- 8 – Designed for [|systems with 4 or 8 processors]
Socket C32 and G34 Opterons use a new four-digit numbering scheme. The first digit refers to the number of CPUs in the target machine:
- 4 – Designed for uniprocessor and dual-processor systems.
- 6 – Designed for dual-processor and four-processor systems.
For all Opterons, the last two digits in the model number indicate the clock frequency of a CPU, a higher number indicating a higher clock frequency. This speed indication is comparable to processors of the same generation if they have the same amount of cores, single-cores and dual-cores have different indications despite sometimes having the same clock frequency.
The suffix HE or EE indicates a high-efficiency/energy-efficiency model having a lower TDP than a standard Opteron. The suffix SE indicates a top-of-the-line model having a higher TDP than a standard Opteron.
Starting from 65 nm fabrication process, the Opteron codenames have been based on Formula 1 hosting cities; AMD has a long term sponsorship with F1's most successful team, Ferrari.
Opteron (130 nm SOI)
; Single-core – SledgeHammer- CPU-Steppings: B3, C0, CG
- L1-Cache: 64 + 64 KB
- L2-Cache: 1024 KB, full speed
- MMX, Extended 3DNow!, SSE, SSE2, AMD64
- Socket 940, 800 MHz HyperTransport
- Registered DDR SDRAM required, ECC possible
- VCore: 1.50 V – 1.55 V
- Max Power : 89 W
- First Release: April 22, 2003
- Clockrate: 1.4-2.4 GHz
Opteron (90 nm SOI, DDR)
- CPU-Steppings: E4
- L1-Cache: 64 + 64 KB
- L2-Cache: 1024 KB, full speed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
- Socket 940, 800 MHz HyperTransport
- Socket 939/Socket 940, 1000 MHz HyperTransport
- Registered DDR SDRAM required for socket 940, ECC possible
- VCore: 1.35 V – 1.4 V
- Max power : 95 W
- NX Bit
- 64-bit segment limit checks for VMware-style binary-translation virtualization.
- Optimized Power Management
- First Release: December 2004
- Clockrate: 1.6 – 3.0 GHz
- CPU-Steppings: E1, E6
- First Release: April 2005
- Clockrate: 1.6-2.8 GHz
- ...
- Socket 939/Socket 940, 1000 MHz HyperTransport
- ...
- NX bit
Opteron (90 nm SOI, DDR2)
- CPU steppings: F2, F3
- L1-Cache: 64 + 64 KB
- L2-Cache: 2 × 1024 KB, full speed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64
- Socket F, 1000 MHz HyperTransport – Opteron 22yy, 82yy
- Socket AM2, 1000 MHz HyperTransport – Opteron 12yy
- VCore: 1.35 V
- Max power : 95 W
- NX bit
- AMD-V Virtualization
- Optimized Power Management
- First release: ?????? 2006
- Clockrate: 1.8-3.2 GHz
Opteron (65 nm SOI)
- CPU steppings: BA, B3
- L1-Cache: 64 + 64 KB per core
- L2-Cache: 512 KB, full speed per core
- L3-Cache: 2048 KB, shared
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, SSE4a, ABM
- Socket F, Socket AM2+, HyperTransport 3.0
- Registered DDR2 SDRAM required, ECC possible
- VCore: 1.2 V
- Max power : 95 Watts
- NX bit
- 2nd-generation AMD-V Virtualization with Rapid Virtualization Indexing
- Split power plane dynamic power management
- First release: September 10, 2007
- Clockrate: 1.7-2.5 GHz
Opteron (45 nm SOI)
- CPU-Steppings: C2
- L3-Cache: 6 MB, shared
- Clockrate: 2.3-2.9 GHz
- HyperTransport 1.0, 3.0
- 20% reduction in idle power consumption
- support for DDR2 800 MHz memory
- support for DDR3 1333 MHz memory
Released June 1, 2009.
- CPU-Steppings: D0
- L3-Cache: 6 MB, shared
- Clockrate: 2.2-2.8 GHz
- HyperTransport 3.0
- HT Assist
- support for DDR2 800 MHz memory
Released March 29, 2010.
- CPU-Steppings: D1
- Multi-chip module consisting of two quad-core dies
- L2-Cache, 8 × 512 KB
- L3-Cache: 2 × 6 MB, shared
- Clockrate: 2.0-2.6 GHz
- Four HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1333 MHz memory
- Socket G34
Released March 29, 2010
- CPU-Steppings: D1
- Multi-chip module consisting of two hex-core dies
- L2-Cache, 12 × 512 KB
- L3-Cache: 2 × 6 MB, shared
- Clockrate: 1.7-2.5 GHz
- Four HyperTransport 3.1 links at 3.2 GHz
- HT Assist
- support for DDR3 1333 MHz memory
- Socket G34
Released June 23, 2010
- CPU-Steppings: D0
- L3-Cache: 6 MB
- Clockrate: 2.2 GHz, 2.6 GHz
- Two HyperTransport links at 3.2 GHz
- HT Assist
- Support for DDR3-1333 memory
- Socket C32
Released June 23, 2010
- CPU-Steppings: D1
- L3-Cache: 6 MB
- Clockrate: 1.7-2.8 GHz
- Two HyperTransport links at 3.2 GHz
- HT Assist
- Support for DDR3-1333 memory
- Socket C32
Opteron (32 nm SOI) – First Generation ''Bulldozer'' Microarchitecture
Released March 20, 2012.
- CPU-Steppings: B2
- Single processor Bulldozer module
- L2-Cache: 2 × 2 MB
- L3-Cache: 4 MB
- Clockrate: 2.5 GHz – 2.7 GHz
- HyperTransport 3
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, up to 3.5 GHz, up to 3.7 GHz
- Supports uniprocessor configurations only
- Socket AM3+
Released March 20, 2012.
- CPU-Steppings: B2
- Single processor Bulldozer module
- L2-Cache: 4 × 2 MB
- L3-Cache: 8MB
- Clockrate: 2.4 GHz
- HyperTransport 3
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, up to 3.5 GHz
- Supports uniprocessor configurations only
- Socket AM3+
Released November 14, 2011.
- CPU-Steppings: B2
- Single die consisting of three dual-core Bulldozer modules
- L2-Cache: 6 MB
- L3-Cache: 8 MB, shared
- Clockrate: 2.7-3.3 GHz
- Two HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support
- Supports up to dual-processor configurations
- Socket C32
Released November 14, 2011.
- CPU-Steppings: B2
- Single die consisting of four dual-core Bulldozer modules
- L2-Cache: 8 MB
- L3-Cache: 8 MB, shared
- Clockrate: 1.6-3.0 GHz
- Two HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support
- Supports up to dual-processor configurations
- Socket C32
Released November 14, 2011.
- CPU-Steppings: B2
- Multi-chip module consisting of two dies, each with one dual-core Bulldozer module
- L2-Cache: 2 × 2 MB
- L3-Cache: 2 × 8 MB, shared
- Clockrate: 3.3 GHz
- HyperTransport 3 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Does not support Turbo CORE
- Supports up to quad-processor configurations
- Socket G34
Released November 14, 2011.
- CPU-Steppings: B2
- Multi-chip module consisting of two dies, each with two dual-core Bulldozer modules
- L2-Cache: 2 × 4 MB
- L3-Cache: 2 × 8 MB, shared
- Clockrate: 2.6, 3.0 GHz
- Four HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support
- Supports up to quad-processor configurations
- Socket G34
Released November 14, 2011.
- CPU-Steppings: B2
- Multi-chip module consisting of two dies, each with three dual-core Bulldozer modules
- L2-Cache: 2 × 6 MB
- L3-Cache: 2 × 8 MB, shared
- Clockrate: 2.4, 2.6 GHz
- Four HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support
- Supports up to quad-processor configurations
- Socket G34
Released November 14, 2011.
- CPU-Steppings: B2
- Multi-chip module consisting of two dies, each with four dual-core Bulldozer modules
- L2-Cache: 2 × 8 MB
- L3-Cache: 2 × 8 MB, shared
- Clockrate: 1.6-2.7 GHz
- Four HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support
- Supports up to quad-processor configurations
- Socket G34
Opteron (32 nm SOI) – ''Piledriver'' microarchitecture
Released December 4, 2012.
- CPU-Steppings: C0
- Single die consisting of two Piledriver modules
- L2-Cache: 2 × 2 MB
- L3-Cache: 8 MB, shared
- Clockrate: 1.9 GHz – 2.8 GHz
- 1 × HyperTransport 3
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, up to 2.5 GHz, up to 3.8 GHz
- Supports uniprocessor configurations only
- Socket AM3+
Released December 4, 2012.
- CPU-Steppings: C0
- Single die consisting of four Piledriver modules
- L2-Cache: 4 × 2 MB
- L3-Cache: 8 MB, shared
- Clockrate: 2.6 GHz
- 1 × HyperTransport 3
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, pp to 3.6 GHz
- Supports uniprocessor configurations only
- Socket AM3+
Released December 4, 2012
- CPU-Steppings: C0
- Single die consisting of two Piledriver modules
- L2-Cache: 2 × 2 MB
- L3-Cache: 8 MB, shared
- Clockrate: 2.2 GHz
- 2 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, up to 3.0 GHz
- Supports up to dual-processor configurations
- Socket C32
Released December 4, 2012
- CPU-Steppings: C0
- Single die consisting of three Piledriver modules
- L2-Cache: 3 × 2 MB
- L3-Cache: 8 MB, shared
- Clockrate: 3.0 GHz – 3.5 GHz
- 2 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, from 3.5 GHz to 3.8 GHz
- Supports up to dual-processor configurations
- Socket C32
Released December 4, 2012
- CPU-Steppings: C0
- Single die consisting of four Piledriver modules
- L2-Cache: 4 × 2 MB
- L3-Cache: 8 MB, shared
- Clockrate: 2.6 GHz – 3.1 GHz
- 2 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, from 3.6 GHz to 3.8 GHz
- Supports up to dual-processor configurations
- Socket C32
Released November 5, 2012.
- CPU-Steppings: C0
- Multi-chip module consisting of two dies, each with one Piledriver module
- L2-Cache: 2 MB per die
- L3-Cache: 2 × 8 MB, shared within each die
- Clockrate: 3.5 GHz
- 4 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Does not support Turbo CORE
- Supports up to quad-processor configurations
- Socket G34
Released November 5, 2012.
- CPU-Steppings: C0
- Multi-chip module consisting of two dies, each with two Piledriver module
- L2-Cache: 2 × 2 MB per die
- L3-Cache: 2 × 8 MB, shared within each die
- Clockrate: 2.8 GHz – 3.2 GHz
- 4 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, from 3.3 GHz to 3.8 GHz
- Supports up to quad-processor configurations
- Socket G34
Released November 5, 2012.
- CPU-Steppings: C0
- Multi-chip module consisting of two dies, each with three Piledriver module
- L2-Cache: 3 × 2 MB per die
- L3-Cache: 2 × 8 MB, shared within each die
- Clockrate: 2.6 GHz – 2.8 GHz
- 4 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, from 3.2 GHz to 3.4 GHz
- Supports up to quad-processor configurations
- Socket G34
Released November 5, 2012.
- CPU-Steppings: C0
- Multi-chip module consisting of two dies, each with four Piledriver module
- L2-Cache: 4 × 2 MB per die
- L3-Cache: 2 × 8 MB, shared within each die
- Clockrate: 1.8 GHz – 2.8 GHz
- 4 × HyperTransport 3.1 at 3.2 GHz
- HT Assist
- support for DDR3 1866 MHz memory
- Turbo CORE support, from 3.1 GHz to 3.5 GHz
- Supports up to quad-processor configurations
- Socket G34
Opteron X (28 nm bulk) – ''Jaguar'' microarchitecture
Released May 29, 2013
- Single SoC with one Jaguar module and integrated I/O
- Configurable CPU frequency and TDP
- L2 Cache: 2MB shared
- CPU frequency: 1.0–2.0 GHz
- Max. TDP: 9–17W
- Support for DDR3-1600 memory
- Socket FT3
Released May 29, 2013
- Single SoC with one Jaguar module, integrated GCN GPU and I/O
- Configurable CPU/GPU frequency and TDP
- L2 Cache: 2MB shared
- CPU frequency: 1.1–1.9 GHz
- GPU frequency: 266–600 MHz
- GPU cores: 128
- Max. TDP: 11–22W
- Support for DDR3-1600 memory
- Socket FT3
Opteron A (28 nm) – ''ARM Cortex-A57'' ARM microarchitecture
A1100-series
The Opteron A1100-series "Seattle" are SoCs based on ARM Cortex-A57 cores that use the ARMv8-A instruction set. They were first released in January 2016.- Cores: 4–8
- Frequency: 1.7–2.0 GHz
- L2 Cache: 2 MB or 4 MB
- L3 Cache: 8 MB
- Thermal Design Power: 25 W or 32 W
- Up to 64 GB DDR3L-1600 and up to 128GB DDR4-1866 with ECC
- SoC peripherals include 14 × SATA 3, 2 × integrated 10 GbE LAN, and eight PCI Express lanes in ×8, ×4, and ×2 configurations
Opteron X (28 nm bulk) – ''Excavator'' microarchitecture
;Dual-core – Toronto
- L2-Cache: 1 MB
- CPU frequency: 1.6 GHz
- Turbo CORE support, 3.0 GHz
- GPU frequency: 800 MHz
- TDP: 12-15W
- support for DDR4 1600 MHz memory
- L2-Cache: 2 × 1 MB
- CPU frequency: 1.8 GHz - 2.1 GHz
- Turbo CORE support, 3.2 GHz - 3.4GHz
- GPU frequency: 800 MHz
- TDP: 12-35W
- support for DDR4 2400 MHz memory
Supercomputers
Several supercomputers using only Opteron processors were ranked in the top 10 systems between 2003 and 2015, notably:
- Red Storm – Sandia National Laboratories – system in November 2006.
- Jaguar – Oak Ridge National Laboratory – various configurations held top 10 positions between 2005 and 2011, including in November 2009 and June 2010.
- Ranger – Texas Advanced Computing Center – system in June 2008.
- Kraken – National Institute for Computational Sciences – system in November 2009.
- Hopper – National Energy Research Scientific Computing Center – system in November 2010.
- IBM Roadrunner – Los Alamos National Laboratory – system in 2008. Composed of Opteron processors with IBM PowerXCell 8i co-processors.
- Titan – Oak Ridge National Laboratory – system in 2012, as of November 2017. Composed of Opteron processors with Nvidia Fermi GPU-based accelerators.
Issues
Opteron without Optimized Power Management
AMD released some Opteron processors without Optimized Power Management support, which use DDR memory. The following table describes those processors without OPM.Max P-state frequency | Min P-state frequency | Model | Package-socket | Core # | TDP | Manufacturing process | Part number |
1400 MHz | N/A | 140 | Socket 940 | 1 | 82.1 | 130 nm | OSA140CEP5AT |
1400 MHz | N/A | 240 | Socket 940 | 1 | 82.1 | 130 nm | OSA240CEP5AU |
1400 MHz | N/A | 840 | Socket 940 | 1 | 82.1 | 130 nm | OSA840CEP5AV |
1600 MHz | N/A | 142 | Socket 940 | 1 | 82.1 | 130 nm | OSA142CEP5AT |
1600 MHz | N/A | 242 | Socket 940 | 1 | 82.1 | 130 nm | OSA242CEP5AU |
1600 MHz | N/A | 842 | Socket 940 | 1 | 82.1 | 130 nm | OSA842CEP5AV |
1600 MHz | N/A | 242 | Socket 940 | 1 | 85.3 | 90 nm | OSA242FAA5BL |
1600 MHz | N/A | 842 | Socket 940 | 1 | 85.3 | 90 nm | OSA842FAA5BM |
1600 MHz | N/A | 260 | Socket 940 | 2 | 55.0 | 90 nm | OSK260FAA6CB |
1600 MHz | N/A | 860 | Socket 940 | 2 | 55.0 | 90 nm | OSK860FAA6CC |
Opteron recall (2006)
AMD recalled some E4 stepping-revision single-core Opteron processors, including ×52 and ×54 models which use DDR memory. The following table describes affected processors, as listed in AMD Opteron ×52 and ×54 Production Notice of 2006.Max P-state frequency | Uni-processor | Dual processor | Multi-processor | Package-socket |
2600 MHz | 152 | 252 | 852 | Socket 940 |
2800 MHz | N/A | 254 | 854 | Socket 940 |
2600 MHz | 152 | N/A | N/A | Socket 939 |
2800 MHz | 154 | N/A | N/A | Socket 939 |
The affected processors may produce inconsistent results if three specific conditions occur simultaneously:
- The execution of floating point-intensive code sequences
- Elevated processor temperatures
- Elevated ambient temperatures