Jaguar (microarchitecture)

Design

• 32 KiB instruction + 32 KiB data L1 cache per core, L1 cache includes parity error detection
• 16-way, 1–2 MiB unified L2 cache shared by two or four cores, L2 cache is protected from errors by the use of error correcting code
• Out-of-order execution and speculative execution
• Integrated memory controller
• Two-way integer execution
• Two-way 128-bit wide floating-point and packed integer execution
• Integer hardware divider
• Consumer processors support two DDR3L DIMMs in one channel at frequencies up to 1600 MHz
• Server processors support two DDR3 DIMMS in one channel at frequencies up to 1600 MHz with ECC
• As a SoC it integrates Fusion controller hub
• Jaguar does not feature clustered multi-thread, meaning that execution resources are not shared between cores

  Instruction set support

Improvements over ''Bobcat''">Bobcat (microarchitecture)">''Bobcat''

• Over 10% increase in clock frequency
• Over 15% improvement in instructions per clock
• Added support for SSE4.1, SSE4.2, AES, CLMUL, MOVBE, AVX, F16C, BMI1
• Up to four CPU cores
• L2 cache is shared between cores
• FPU datapath width increased to 128-bit
• Added hardware integer divider
• Enhanced cache prefetchers
• Doubled bandwidth of load-store units
• C6 and CC6 low power states with lower entry and exit latency
• Smaller, 3.1 mm² area per core
• Integrated Fusion controller hub
• Video Coding Engine

  Features

Processors

Consoles

Desktop

Desktop/Mobile

Server

Opteron X1100-series "Kyoto" (28 nm)

Opteron X2100-series "Kyoto" (28 nm)

Embedded

Jaguar derivative and successor