AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions". Since an initialism cannot be trademarked, this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.
Technical details
MMX defines eight registers, called MM0 through MM7, and operations that operate on them. Each register is 64 bits wide and can be used to hold either 64-bit integers, or multiple smaller integers in a "packed" format: a single instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once. MMX provides only integer operations. When originally developed, for the Intel i860, the use of integer math made sense, but as graphics cards that did much of this became common, integer SIMD in the CPU became somewhat redundant for graphical applications. On the other hand, the saturation arithmetic operations in MMX could significantly speed up some digital signal processing applications. To avoid compatibility problems with the context switch mechanisms in existing operating systems, the MMX registers are aliases for the existing x87FPU registers, which context switches would already save and restore. Unlike the x87 registers, which behave like a stack, the MMX registers are each directly addressable. Any operation involving the floating point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating point and SIMD operations in the same application. To maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible. Each 64-bit MMX register corresponds to the mantissa part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and these bits are all set to ones, making them NaNs or infinities in the floating point representation. This can be used by applications to decide whether a particular register's content is intended as floating point or SIMD data.
, a competing x86 microprocessor vendor, enhanced Intel's MMX with their own 3DNow! instruction set. 3DNow is best known for adding single-precision floating-point support to the SIMD instruction-set, among other integer and more general enhancements. Following MMX, Intel's next major x86 extension was the SSE, introduced with the Pentium-III family in 1999, roughly a year after AMD's 3DNow! was introduced. SSE addressed the core shortcomings of MMX by creating a new 128-bit wide register file and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations ; integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops. SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMX opcodes to use XMM register operands, extended to even wider YMM and ZMM registers by later SSE revisions.
MMX in embedded applications
Intel's and Marvell's XScalemicroprocessor core starting with PXA270 include an SIMD instruction set extension to the ARM core called iwMMXt whose functions are similar to those of the IA-32 MMX extension. iwMMXt stands for "Intel Wireless MMX Technology". It provides arithmetic and logic operations on 64-bit integer numbers. The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA. Later versions of Marvell's ARM processors support both WMMX and WMMX2 opcodes.
