The Power ISA is an instruction set architecture developed by the OpenPOWER Foundation, led by IBM. It was originally developed by the now defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category; each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category. Power ISA is a RISCload/store architecture. It has multiple sets of registers:
* thirty-two 64-bit floating-point registers as part of the VSRs for floating point operations.
* thirty-two 128-bit vector registers as part of the VSRs for vector operations.
Eight 4-bit condition register fields for comparison and control flow.
Special registers: counter register, link register, time base, alternate time base, accumulator, status registers.
Instructions have a length of 32 bits, with the exception of the VLE subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precisionIEEE-754 compliant floating point operations are supported, including additional fused multiply–add and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction. Power ISA has support for Harvardcache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, as well as support for both 32-bit and 64-bit addressing. Different modes of operation include user, supervisor and hypervisor.
Misc – floating point, vector, signal processing, cache locking, decimal floating point, etc.
Books
The Power ISA specification is divided into five parts, called "books":
Book I – User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
Book II – Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
Book III – Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It's divided into two parts.
*Book III-S – Defines the supervisor instructions used for general purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
*Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big endian byte ordering.
Specifications
Power ISA v.2.03
The specification for Power ISA v.2.03 is based on the former PowerPC ISA v.2.02 in POWER5+ and the Book E extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension. Compliant cores
The specification for Power ISA v.2.04 was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling. Compliant cores
All cores that comply with previous versions of the Power ISA
The specification for Power ISA v.2.05 was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic and server hypervisor improvements. Compliant cores
All cores that comply with previous versions of the Power ISA
The specification for Power ISA v.2.06 was released in February 2009, and revised in July 2010. It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions. Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations. The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features. Compliant cores
All cores that comply with previous versions of the Power ISA
The specification for Power ISA v.2.07 was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functionality, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities, along with AES and Galois Counter Mode, SHA-224, SHA-256, SHA-384 and SHA-512 cryptographic extensions and cyclic redundancy check algorithms. The spec was revised in April 2015 to the Power ISA v.2.07 B spec. Compliant cores
All cores that comply with previous versions of the Power ISA
The specification for Power ISA v.3.0 was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a random number generator, hardware-assisted garbage collection and hardware-enforced trusted computing. The spec was revised in March 2017 to the Power ISA v.3.0 B spec. Compliant cores
All cores that comply with previous versions of the Power ISA
The specification for Power ISA v.3.1 was released in May 2020. Mainly giving support for new functionality introduced in POWER10, but also includes the notion of optionality to the PowerISA specification. Instructions can now be eight bytes long, "prefixed instructions", compared to the usual four byte "word instructions". A lot of new functionality to SIMD and VSX instructions are also added. Compliant cores
All cores that comply with previous versions of the Power ISA
