There are three versions of the e500 core, namely the original e500v1, the e500v2 and the e500mc. A 64-bit evolution of the e500mc core is called the e5500 core and was introduced in 2010, and a subsequent e6500 core added multithreading capabilities in 2012.
e500v1
Support for the SPE extensions. The integer register file is extended to a width of 64-bits. The non-SPE instructions only access and write to the low 32-bits. However the SIMD SPE instructions read and write from the full 64-bits. These extensions overlap with the string and AltiVec instructions.
Support for SPESFP. This is a new floating point unit that is distinct from the classic FPU, the latter of which is lacking in e500v1 and e500v2. SPESFP uses the integer register file. It is not completely IEEE754 compliant.
e500v2
Key improvements in the e500v2 over the e500v1 include:
Increase from 32-bit to 36-bit physical address space. This change means that e500v2-based devices often use a more advanced board support package than e500v1-based devices, as various peripheral units have moved to physical addresses higher than 4 GiB.
Addition of 1 GiB and 4 GiB variable-page sizes
Addition of DPESFP support. Building on top of SPESFP, these instructions access both halves of the 64-bit integer register.
Doubling in size and associativity of the MMU's second-level 4K-page array
Increase from 3 to 5 maximum outstanding data cache misses
Addition of the Alternate Time Base for cycle-granularity timestamps
e500mc
Freescale introduced the e500mc in the QorIQ family of chips in June 2008. The e500mc has the following features:
Power ISA v.2.06, which includes hypervisor and virtualization functionality for embedded platforms.
SPE, SPESFP, and DPESFP are all removed, and the integer register file is back to 32 bits.
Support anything from two to more than 32 cores on a single chip.
Supports the CoreNet communications fabric for connecting cores and datapath accelerators.
e500mc cores have private L2 caches but typically share other facilities like L3 caches, memory controllers, application specific acceleration cores, I/O and such.
Applications
PowerQUICC
All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores, most of them on the latter.
QorIQ
In June 2008 Freescale announced the QorIQ brand, microprocessors based on the e500 family of cores.
