The MicroBlaze is a soft microprocessor core designed for Xilinxfield-programmable gate arrays. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
Overview
In terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the AXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the CoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly. For access to local-memory, MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are supported through dedicated AXI4-Stream connections. The coprocessor interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module. Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth, embedded peripherals, memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area. The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700 MHz. Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed. This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements. With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core.
Vivado
Xilinx's Vivado Design Suite is the development environment for building current MicroBlaze embedded processor systems in Xilinx FPGAs. Older versions used Xilinx's EDK development package. Designers use the Vivado IP Integrator to configure and build the hardware specification of their embedded system The IP Integrator converts the designer's block design into a synthesizeable RTL description, and automates the implementation of the embedded system For the MicroBlaze core, Vivado generates an encrypted netlist. The SDK handles the software that will execute on the embedded system. Powered by the GNU toolchain, the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx's tools provides the possibility of running software in simulation, or using a suitable FPGA-board to download and execute on the actual system. Purchasers of Vivado are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices. Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required.
Open source
In June 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux kernel source tree. This work was performed by Michal Simek and supported by PetaLogix and Xilinx. As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6 Support was added to LLVM in April 2010, but subsequently removed in July 2013 due to a lack of maintainer.
