MyHDL


MyHDL is a Python based hardware description language.
Features of MyHDL include:
MyHDL is developed by Jan Decaluwe.

Conversion examples

Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.
A small combinatorial design
The example is a small combinatorial design, more specifically the binary to Gray code converter:

def bin2gray:
"""Gray encoder.
B -- input intbv signal, binary encoded
G -- output intbv signal, gray encoded
width -- bit width
"""
@always_comb
def logic:
Bext = intbv
Bext = B
for i in range:
G.next = Bext ^ Bext
return logic

You can create an instance and convert to Verilog and VHDL as follows:

width = 8
B = Signal
G = Signal
bin2gray_inst = toVerilog
bin2gray_inst = toVHDL

The generated Verilog code looks as follows:

module bin2gray ;
input B;
output G;
reg G;
always @ begin: BIN2GRAY_LOGIC
integer i;
reg Bext;
Bext = 9'h0;
Bext = B;
for begin
G <= ;
end
end
endmodule

The generated VHDL code looks as follows:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06.all;
entity bin2gray is
port ;
G: out unsigned
);
end entity bin2gray;
architecture MyHDL of bin2gray is
begin
BIN2GRAY_LOGIC: process is
variable Bext: unsigned;
begin
Bext := to_unsigned;
Bext := resize;
for i in 0 to 8-1 loop
G <= ) xor Bext);
end loop;
end process BIN2GRAY_LOGIC;
end architecture MyHDL;