List of Intel CPU microarchitectures


The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model and Process-Architecture-Optimization model.

x86 microarchitectures

Note: Intel Atom processors are in italic.
YearMicro-architecturePipeline stagesMax
Clock
Tech
process
19788086 253000
1982186 2253000
1982286 3251500
1985386 3331500
1989486 51001000
1993P5 5200800, 600, 350
1995P6 14 450500, 350, 250
1997P5 6233350
1999P6 12 1400250, 180, 130
2000NetBurst
20 unified with branch prediction2000180
2002NetBurst
20 unified with branch prediction3466130
2003Pentium M
Enhanced Pentium M 		10 2333130, 90, 65
2004NetBurst
31 unified with branch prediction380090
2006Intel Core12 300065
2007Penryn 12 333345
2008Nehalem20 unified 360045
2008Bonnell16 210045
2010Westmere 20 unified 373032
2011Saltwell 16 213032
2011Sandy Bridge14 400032
2012Ivy Bridge 14 410022
2013Silvermont14–17 267022
2013Haswell14 440022
2014Broadwell 14 370014
2015Airmont 14–17 264014
2015Skylake14 420014
2016Goldmont20 unified with branch prediction260014
2016Kaby Lake14 450014
2017Coffee Lake14 500014
2017Goldmont Plus? 20 unified with branch prediction ?280014
2018Cannon Lake 14 320010
2018Whiskey Lake14 480014
2018Amber Lake14 420014
2019Cascade Lake14 440014
2019Comet Lake14 530014
2019Sunny Cove 14–20390010
2020Tremont 10
Cooper Lake14 14
Willow Cove 10
Golden Cove 10
Gracemont10
Meteor Lake7

; 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer.
; 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
; 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
; i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
; i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit, 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
; P5: original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
; P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension ".
; NetBurst:commonly referred to as P7 although its internal name was P68. Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX bit to implement executable-space protection.
; Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
; Intel Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
; Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
; Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors.
; Larrabee : multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC.
; Sandy Bridge:32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007. First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
; Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
; Haswell: 22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including FMA.
; Skylake:14 nm microarchitecture, released August 5, 2015.
; Goldmont: 14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors, released April 2016.
; Tremont:10 nm Atom microarchitecture iteration after Goldmont Plus.
;Palm Cove: After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.
Successor to the Skylake core, first consumer core to include the AVX-512 instruction set.
; Sunny Cove:Successor to the Palm Cove core, first core to include hardware acceleration for SHA hashing algorithms.
; Willow Cove:Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.
; Golden Cove:Successor to the Willow Cove core, includes improvements to single threaded performance, AI performance, network and 5G performance and new security features.
; Ocean Cove:Successor to the Golden Cove core.

Itanium microarchitectures

; : original Itanium microarchitecture. Used only in the first Itanium microprocessors.
; : enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
; Montecito: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
; Tukwila: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
; : Itanium processor featuring a new microarchitecture.
; : the last Itanium microarchitecture. It has slightly higher clock speed than Poulson.

Roadmap

Pentium 4 / Core lines

Hybrid

Atom lines