Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip made by Intel. They allow only one thread per core. The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum in Shenzhen, China, April 2016. The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.
Design
Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers. Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake. The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:
An out-of-order execution engine with a 3-wide superscalar pipeline. Specifically:
Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle. The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput and many other SIMD instructions with doubled throughput.
Throughput and latency of instructions for accelerating encryption/decryption and carry-less multiplication have been improved significantly in the Goldmont microarchitecture.
Integrated Sensor Hub which can sample and combine data from individual sensors and operate independently when the host platform is in a low power state
Similar to previous Silvermont generation design flaws were found in processor circuitry resulting in cease of operation when processors are actively used for several years. Errata named APL46 "System May Experience Inability to Boot or May Cease Operation" was added to documentation in June 2017 stating that Low pin count, Real time clock, SD card and GPIO interfaces may stop functioning. Mitigations were found to limit impact on systems. Firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface which in turn decreases LPC bus degradation - some systems are however not compatible with this new firmware. It is recommended not to use SD card as a boot device and to remove the card from the system when not in use, other possible solution being using only UHS-I cards and operating them at 1.8V. Congatec also states the issues impact USB buses and eMMC, although those are not mentioned in Intel's public documentation. USB should have a maximum of 12% active time and there is a 60TB transmit traffic life expectancy over the lifetime of the port. eMMC should have a maximum of 33% active time and should be set to D3 device low power state by the operating system when not in use. Newer designs such as Atom C3000 Denverton do not seem to be affected.
