Intel 8087


The Intel 8087, announced in 1980, was the first x87 floating-point coprocessor for the 8086 line of microprocessors.
The purpose of the 8087 was to speed up computations for floating-point arithmetic, such as addition, subtraction, multiplication, division, and square root. It also computed transcendental functions such as exponential, logarithmic or trigonometric calculations, and besides floating-point it could also operate on large binary and decimal integers. The performance enhancements were from approximately 20% to over 500%, depending on the specific application. The 8087 could perform about 50,000 FLOPS using around 2.4 watts. Only arithmetic operations benefited from installation of an 8087; computers used only with such applications as word processing, for example, would not benefit from the extra expense and power consumption of an 8087.
The 8087 was an advanced IC for its time, pushing the limits of manufacturing technology of the period. Initial yields were extremely low.
The sales of the 8087 received a significant boost when IBM included a coprocessor socket on the IBM PC motherboard. Due to a shortage of chips, IBM did not actually offer the 8087 as an option for the PC until it had been on the market for six months. Development of the 8087 led to the IEEE 754-1985 standard for floating-point arithmetic. There were later x87 coprocessors for the 80186, 80286, 80386, and 80386SX processors. Starting with the 80486, the later Intel x86 processors did not use a separate floating-point coprocessor; floating-point functions were provided integrated with the processor.

Design and development

Intel had previously manufactured the 8231 Arithmetic processing unit, and the 8232 Floating Point Processor. These were designed for use with 8080 or similar processors and used an 8-bit data bus. They were interfaced to a host system either through programmed I/O or a DMA controller.
The 8087 was initially conceived by Bill Pohlman, the engineering manager at Intel who oversaw the development of the 8086 chip. Bill took steps to be sure that the 8086 chip could support a yet-to-be-developed math chip.
In 1977 Pohlman got the go ahead to design the 8087 math chip. Bruce Ravenel was assigned as architect, and John Palmer was hired to be co-architect and mathematician for the project. The two came up with a revolutionary design with 64 bits of mantissa and 16 bits of exponent for the longest-format real number, with a stack architecture CPU and 8 80-bit stack registers, with a computationally rich instruction set. The design solved a few outstanding known problems in numerical computing and numerical software: rounding-error problems were eliminated for 64-bit operands, and numerical mode conversions were solved for all 64-bit numbers. Palmer credited William Kahan's writings on floating point as a significant influence on their design.
The 8087 design initially met a cool reception in Santa Clara due to its aggressive design. Eventually, the design was assigned to Intel Israel, and Rafi Nave was assigned to lead the implementation of the chip. Palmer, Ravenel and Nave were awarded patents for the design. Robert Koehler and John Bayliss were also awarded a patent for the technique where some instructions with a particular bit pattern were offloaded to the coprocessor.
The 8087 had 45,000 transistors and was manufactured as a 3 μm depletion-load HMOS circuit. It worked in tandem with the 8086 or 8088 and introduced about 60 new instructions. Most 8087 assembly mnemonics begin with F, such as FADD, FMUL, FCOM and so on, making them easily distinguishable from 8086 instructions. The binary encodings for all 8087 instructions begin with the bit pattern 11011, decimal 27, the same as the ASCII character ESC, although in the higher-order bits of a byte; similar instruction prefixes are also sometimes referred to as "escape codes". The instruction mnemonic assigned by Intel for these coprocessor instructions is "ESC".
When the 8086 or 8088 CPU executed the ESC instruction, if the second byte specified a memory operand, the CPU would execute a bus cycle to read one word from the memory location specified in the instruction, but it would not store the read operand into any CPU register or perform any operation on it; the 8087 would observe the bus and decode the instruction stream in sync with the 8086, recognizing the coprocessor instructions meant for itself. For an 8087 instruction with a memory operand, if the instruction called for the operand to be read, the 8087 would take the word of data read by the main CPU from the data bus. If the operand to be read was longer than one word, the 8087 would also copy the address from the address bus; then, after completion of the data read cycle driven by the CPU, the 8087 would immediately use DMA to take control of the bus and transfer the additional bytes of the operand itself. If an 8087 instruction with a memory operand called for that operand to be written, the 8087 would ignore the read word on the data bus and just copy the address, then request DMA and write the entire operand, in the same way that it would read the end of an extended operand. In this way, the main CPU maintained general control of the bus and bus timing, while the 8087 handled all other aspects of execution of coprocessor instructions, except for brief DMA periods when the 8087 would take over the bus to read or write operands to/from its own internal registers. As a consequence of this design, the 8087 could only operate on operands taken either from memory or from its own registers, and any exchange of data between the 8087 and the 8086 or 8088 was only through RAM.
The main CPU program continued to execute while the 8087 executed an instruction; from the perspective of the main 8086 or 8088 CPU, a coprocessor instruction took only as long as the processing of the opcode and any memory operand cycle, after which the CPU would begin executing the next instruction of the program. Thus, a system with an 8087 was capable of true parallel processing, performing one operation in the integer ALU of the main CPU while at the same time performing a floating-point operation in the 8087 coprocessor. Since the 8086 or 8088 exclusively controlled the instruction flow and timing and had no direct access to the internal status of the 8087, and because the 8087 could execute only one instruction at a time, programs for the combined 8086/8087 or 8088/8087 system had to ensure that the 8087 had time to complete the last instruction issued to it before it was issued another one. The WAIT instruction was provided for this purpose, and most assemblers implicitly asserted a WAIT instruction before each instance of most floating-point coprocessor instructions. The WAIT instruction waited for the −TEST input pin of the 8086/8088 to be asserted, and this pin was connected to the BUSY pin of the 8087 in all systems that had an 8087.
Because the instruction prefetch queues of the 8086 and 8088 make the time when an instruction is executed not always the same as the time it is fetched, a coprocessor such as the 8087 cannot determine when an instruction for itself is the next instruction to be executed purely by watching the CPU bus. The 8086 and 8088 have two queue status signals connected to the coprocessor to allow it to synchronize with the CPU's internal timing of execution of instructions from its prefetch queue. The 8087 maintains its own identical prefetch queue, from which it reads the coprocessor opcodes that it actually executes. Because the 8086 and 8088 prefetch queues have different sizes and different management algorithms, the 8087 determines which type of CPU it is attached to by observing a certain CPU bus line when the system is reset, and the 8087 adjusts its internal instruction queue accordingly. The redundant duplication of prefetch queue hardware in the CPU and the coprocessor is inefficient in terms of power usage and total die area, but it allowed the coprocessor interface to use very few dedicated IC pins, which was important. At the time when the 8086, which defined the coprocessor interface, was introduced, IC packages with more than 40 pins were rare, expensive, and wrangled with problems such as excessive lead capacitance, a major limiting factor for signalling speeds.
The coprocessor operation codes are encoded in 6 bits across 2 bytes, beginning with the escape sequence:
┌───────────┬───────────┐
│ 1101 1xxx │ mmxx xrrr │
└───────────┴───────────┘
The first three "x" bits are the first three bits of the floating-point opcode. Then two "m" bits, then the latter half three bits of the floating-point opcode, followed by three "r" bits. The "m" and "r" bits specify the addressing-mode information.
Application programs had to be written to make use of the special floating-point instructions. At run time, software could detect the coprocessor and use it for floating-point operations. When detected absent, similar floating-point functions had to be calculated in software, or the whole coprocessor could be emulated in software for more precise numerical compatibility.

Registers

The x87 family does not use a directly addressable register set such as the main registers of the x86 processors; instead, the x87 registers form an eight-level deep stack structure ranging from st0 to st7, where st0 is the top. The x87 instructions operate by pushing, calculating, and popping values on this stack. However, dyadic operations such as FADD, FMUL, FCMP, and so on may either implicitly use the topmost st0 and st1 or may use st0 together with an explicit memory operand or register; the st0 register may thus be used as an accumulator and can also be exchanged with any of the eight stack registers using an instruction called FXCH stX. This makes the x87 stack usable as seven freely addressable registers plus an accumulator. This is especially applicable on superscalar x86 processors, where these exchange instructions are optimized down to a zero-clock penalty.

IEEE floating-point standard

When Intel designed the 8087, it aimed to make a standard floating-point format for future designs. An important aspect of the 8087 from a historical perspective was that it became the basis for the IEEE 754 floating-point standard. The 8087 did not implement the eventual IEEE 754 standard in all its details, as the standard was not finished until 1985, but the 80387 did. The 8087 provided two basic 32/64-bit floating-point data types and an additional extended 80-bit internal temporary format to improve accuracy over large and complex calculations. Apart from this, the 8087 offered an 80-bit/18-digit packed BCD format and 16-, 32-, and 64-bit integer data types.

Infinity

The 8087 handles infinity values by either affine closure or projective closure. With affine closure, positive and negative infinities are treated as different values. With projective closure, infinity is treated as an unsigned representation for very small or very large numbers. These two methods of handling infinity were incorporated into the draft version of the IEEE 754 floating-point standard. However, projective closure was dropped from the later formal issue of IEEE 754-1985. The 80287 retained projective closure as an option, but the 80387 and subsequent floating-point processors only supported affine closure.

Coprocessor interface

The 8087 differed from subsequent Intel coprocessors in that it was directly connected to the address and data buses. The 8087 looked for instructions that commenced with the "11011" sequence and acted on them, immediately requesting DMA from the main CPU as necessary to access memory operands longer than one word, then immediately releasing bus control back to the main CPU. The coprocessor did not hold up execution of the program until the coprocessor instruction was complete, and the program had to explicitly synchronize the two processors, as explained above. There was a potential crash problem if the coprocessor instruction failed to decode to one that the coprocessor understood. Intel's later coprocessors did not connect to the buses in the same way, but received instructions through the main processor I/O ports. This yielded an execution time penalty, but the potential crash problem was avoided because the main processor would ignore the instruction if the coprocessor refused to accept it. The 8087 was able to detect whether it was connected to an 8088 or an 8086 by monitoring the data bus during the reset cycle.
The 8087 was, in theory, capable of working concurrently while the 8086/8 processes additional instructions. In practice, there was the potential for program failure if the coprocessor issued a new instruction before the last one had completed. The assembler would automatically insert an FWAIT instruction after every coprocessor opcode, forcing the 8086/8 to halt execution until the 8087 signalled that it had finished. This limitation was removed from later designs.

Models and second sources

Intel 8087 coprocessors were fabricated in two variants: one with ceramic side-brazed DIP and one in hermetic DIP, and were designed to operate in the following temperature ranges:
All models of the 8087 had a 40-pin DIP package and operated on 5 volts, consuming around 2.4 watts. Unlike later Intel coprocessors, the 8087 had to run at the same clock speed as the main processor. Suffixes on the part number identified the clock speed:
Model numberFrequency
Intel 80875 MHz
Intel 8087-110 MHz
Intel 8087-28 MHz
Intel 8087-34 MHz
Intel 8087-66 MHz

The part was second-sourced by AMD as AMD 8087 and by Cyrix as Cyrix 8087.
The clone K1810WM87 of the 8087 was produced in the Soviet Union.

Successors

Just as the 8088 and 8086 processors were superseded by later parts, so was the 8087 superseded. Other Intel coprocessors were the 80287, 80387, and the 80187. Starting with the 80486, the later Intel processors did not use a separate floating-point coprocessor; virtually all included it on the main processor die, with the significant exception of the 80486SX, which was a modified 80486DX with the FPU disabled. The 80487 was in fact a full-blown 80486DX chip with an extra pin. When installed, it disabled the 80486SX CPU. The 80486DX, Pentium, and later processors include floating-point functionality on the CPU core.

Complete FPU instruction set of the 8087

Abbreviations:
Table contains complete FPU instruction set of 8087, 80287, 80387 and the last extension on Pentium-based FPUs.
OpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemo
D800FADD f32D808FMUL f32D810FCOM f32D818FCOMP f32D820FSUB f32D828FSUBR f32D830FDIV f32D838FDIVR f32
D801FADD f32D809FMUL f32D811FCOM f32D819FCOMP f32D821FSUB f32D829FSUBR f32D831FDIV f32D839FDIVR f32
D802FADD f32D80AFMUL f32D812FCOM f32D81AFCOMP f32D822FSUB f32D82AFSUBR f32D832FDIV f32D83AFDIVR f32
D803FADD f32D80BFMUL f32D813FCOM f32D81BFCOMP f32D823FSUB f32D82BFSUBR f32D833FDIV f32D83BFDIVR f32
D804FADD f32D80CFMUL f32D814FCOM f32D81CFCOMP f32D824FSUB f32D82CFSUBR f32D834FDIV f32D83CFDIVR f32
D805FADD f32D80DFMUL f32D815FCOM f32D81DFCOMP f32D825FSUB f32D82DFSUBR f32D835FDIV f32D83DFDIVR f32
D806nnFADD f32D80EnnFMUL f32D816nnFCOM f32D81EnnFCOMP f32D826nnFSUB f32D82EnnFSUBR f32D836nnFDIV f32D83EnnFDIVR f32
D807FADD f32D80FFMUL f32D817FCOM f32D81FFCOMP f32D827FSUB f32D82FFSUBR f32D837FDIV f32D83FFDIVR f32
D840nFADD f32D848nFMUL f32D850nFCOM f32D858nFCOMP f32D860nFSUB f32D868nFSUBR f32D870nFDIV f32D878nFDIVR f32
D841nFADD f32D849nFMUL f32D851nFCOM f32D859nFCOMP f32D861nFSUB f32D869nFSUBR f32D871nFDIV f32D879nFDIVR f32
D842nFADD f32D84AnFMUL f32D852nFCOM f32D85AnFCOMP f32D862nFSUB f32D86AnFSUBR f32D872nFDIV f32D87AnFDIVR f32
D843nFADD f32D84BnFMUL f32D853nFCOM f32D85BnFCOMP f32D863nFSUB f32D86BnFSUBR f32D873nFDIV f32D87BnFDIVR f32
D844nFADD f32D84CnFMUL f32D854nFCOM f32D85CnFCOMP f32D864nFSUB f32D86CnFSUBR f32D874nFDIV f32D87CnFDIVR f32
D845nFADD f32D84DnFMUL f32D855nFCOM f32D85DnFCOMP f32D865nFSUB f32D86DnFSUBR f32D875nFDIV f32D87DnFDIVR f32
D846nFADD f32D84EnFMUL f32D856nFCOM f32D85EnFCOMP f32D866nFSUB f32D86EnFSUBR f32D876nFDIV f32D87EnFDIVR f32
D847nFADD f32D84FnFMUL f32D857nFCOM f32D85FnFCOMP f32D867nFSUB f32D86FnFSUBR f32D877nFDIV f32D87FnFDIVR f32
D880nnFADD f32D888nnFMUL f32D890nnFCOM f32D898nnFCOMP f32D8A0nnFSUB f32D8A8nnFSUBR f32D8B0nnFDIV f32D8B8nnFDIVR f32
D881nnFADD f32D889nnFMUL f32D891nnFCOM f32D899nnFCOMP f32D8A1nnFSUB f32D8A9nnFSUBR f32D8B1nnFDIV f32D8B9nnFDIVR f32
D882nnFADD f32D88AnnFMUL f32D892nnFCOM f32D89AnnFCOMP f32D8A2nnFSUB f32D8AAnnFSUBR f32D8B2nnFDIV f32D8BAnnFDIVR f32
D883nnFADD f32D88BnnFMUL f32D893nnFCOM f32D89BnnFCOMP f32D8A3nnFSUB f32D8ABnnFSUBR f32D8B3nnFDIV f32D8BBnnFDIVR f32
D884nnFADD f32D88CnnFMUL f32D894nnFCOM f32D89CnnFCOMP f32D8A4nnFSUB f32D8ACnnFSUBR f32D8B4nnFDIV f32D8BCnnFDIVR f32
D885nnFADD f32D88DnnFMUL f32D895nnFCOM f32D89DnnFCOMP f32D8A5nnFSUB f32D8ADnnFSUBR f32D8B5nnFDIV f32D8BDnnFDIVR f32
D886nnFADD f32D88EnnFMUL f32D896nnFCOM f32D89EnnFCOMP f32D8A6nnFSUB f32D8AEnnFSUBR f32D8B6nnFDIV f32D8BEnnFDIVR f32
D887nnFADD f32D88FnnFMUL f32D897nnFCOM f32D89FnnFCOMP f32D8A7nnFSUB f32D8AFnnFSUBR f32D8B7nnFDIV f32D8BFnnFDIVR f32
DC00FADD f64DC08FMUL f64DC10FCOM f64DC18FCOMP f64DC20FSUB f64DC28FSUBR f64DC30FDIV f64DC38FDIVR f64
DC01FADD f64DC09FMUL f64DC11FCOM f64DC19FCOMP f64DC21FSUB f64DC29FSUBR f64DC31FDIV f64DC39FDIVR f64
DC02FADD f64DC0AFMUL f64DC12FCOM f64DC1AFCOMP f64DC22FSUB f64DC2AFSUBR f64DC32FDIV f64DC3AFDIVR f64
DC03FADD f64DC0BFMUL f64DC13FCOM f64DC1BFCOMP f64DC23FSUB f64DC2BFSUBR f64DC33FDIV f64DC3BFDIVR f64
DC04FADD f64DC0CFMUL f64DC14FCOM f64DC1CFCOMP f64DC24FSUB f64DC2CFSUBR f64DC34FDIV f64DC3CFDIVR f64
DC05FADD f64DC0DFMUL f64DC15FCOM f64DC1DFCOMP f64DC25FSUB f64DC2DFSUBR f64DC35FDIV f64DC3DFDIVR f64
DC06nnFADD f64DC0EnnFMUL f64DC16nnFCOM f64DC1EnnFCOMP f64DC26nnFSUB f64DC2EnnFSUBR f64DC36nnFDIV f64DC3EnnFDIVR f64
DC07FADD f64DC0FFMUL f64DC17FCOM f64DC1FFCOMP f64DC27FSUB f64DC2FFSUBR f64DC37FDIV f64DC3FFDIVR f64
DC40nFADD f64DC48nFMUL f64DC50nFCOM f64DC58nFCOMP f64DC60nFSUB f64DC68nFSUBR f64DC70nFDIV f64DC78nFDIVR f64
DC41nFADD f64DC49nFMUL f64DC51nFCOM f64DC59nFCOMP f64DC61nFSUB f64DC69nFSUBR f64DC71nFDIV f64DC79nFDIVR f64
DC42nFADD f64DC4AnFMUL f64DC52nFCOM f64DC5AnFCOMP f64DC62nFSUB f64DC6AnFSUBR f64DC72nFDIV f64DC7AnFDIVR f64
DC43nFADD f64DC4BnFMUL f64DC53nFCOM f64DC5BnFCOMP f64DC63nFSUB f64DC6BnFSUBR f64DC73nFDIV f64DC7BnFDIVR f64
DC44nFADD f64DC4CnFMUL f64DC54nFCOM f64DC5CnFCOMP f64DC64nFSUB f64DC6CnFSUBR f64DC74nFDIV f64DC7CnFDIVR f64
DC45nFADD f64DC4DnFMUL f64DC55nFCOM f64DC5DnFCOMP f64DC65nFSUB f64DC6DnFSUBR f64DC75nFDIV f64DC7DnFDIVR f64
DC46nFADD f64DC4EnFMUL f64DC56nFCOM f64DC5EnFCOMP f64DC66nFSUB f64DC6EnFSUBR f64DC76nFDIV f64DC7EnFDIVR f64
DC47nFADD f64DC4FnFMUL f64DC57nFCOM f64DC5FnFCOMP f64DC67nFSUB f64DC6FnFSUBR f64DC77nFDIV f64DC7FnFDIVR f64
DC80nnFADD f64DC88nnFMUL f64DC90nnFCOM f64DC98nnFCOMP f64DCA0nnFSUB f64DCA8nnFSUBR f64DCB0nnFDIV f64DCB8nnFDIVR f64
DC81nnFADD f64DC89nnFMUL f64DC91nnFCOM f64DC99nnFCOMP f64DCA1nnFSUB f64DCA9nnFSUBR f64DCB1nnFDIV f64DCB9nnFDIVR f64
DC82nnFADD f64DC8AnnFMUL f64DC92nnFCOM f64DC9AnnFCOMP f64DCA2nnFSUB f64DCAAnnFSUBR f64DCB2nnFDIV f64DCBAnnFDIVR f64
DC83nnFADD f64DC8BnnFMUL f64DC93nnFCOM f64DC9BnnFCOMP f64DCA3nnFSUB f64DCABnnFSUBR f64DCB3nnFDIV f64DCBBnnFDIVR f64
DC84nnFADD f64DC8CnnFMUL f64DC94nnFCOM f64DC9CnnFCOMP f64DCA4nnFSUB f64DCACnnFSUBR f64DCB4nnFDIV f64DCBCnnFDIVR f64
DC85nnFADD f64DC8DnnFMUL f64DC95nnFCOM f64DC9DnnFCOMP f64DCA5nnFSUB f64DCADnnFSUBR f64DCB5nnFDIV f64DCBDnnFDIVR f64
DC86nnFADD f64DC8EnnFMUL f64DC96nnFCOM f64DC9EnnFCOMP f64DCA6nnFSUB f64DCAEnnFSUBR f64DCB6nnFDIV f64DCBEnnFDIVR f64
DC87nnFADD f64DC8FnnFMUL f64DC97nnFCOM f64DC9FnnFCOMP f64DCA7nnFSUB f64DCAFnnFSUBR f64DCB7nnFDIV f64DCBFnnFDIVR f64
DE00FIADD i16DE08FIMUL i16DE10FICOM i16DE18FICOMP i16DE20FISUB i16DE28FISUBR i16DE30FIDIV i16DE38FIDIVR i16
DE01FIADD i16DE09FIMUL i16DE11FICOM i16DE19FICOMP i16DE21FISUB i16DE29FISUBR i16DE31FIDIV i16DE39FIDIVR i16
DE02FIADD i16DE0AFIMUL i16DE12FICOM i16DE1AFICOMP i16DE22FISUB i16DE2AFISUBR i16DE32FIDIV i16DE3AFIDIVR i16
DE03FIADD i16DE0BFIMUL i16DE13FICOM i16DE1BFICOMP i16DE23FISUB i16DE2BFISUBR i16DE33FIDIV i16DE3BFIDIVR i16
DE04FIADD i16DE0CFIMUL i16DE14FICOM i16DE1CFICOMP i16DE24FISUB i16DE2CFISUBR i16DE34FIDIV i16DE3CFIDIVR i16
DE05FIADD i16DE0DFIMUL i16DE15FICOM i16DE1DFICOMP i16DE25FISUB i16DE2DFISUBR i16DE35FIDIV i16DE3DFIDIVR i16
DE06nnFIADD i16DE0EnnFIMUL i16DE16nnFICOM i16DE1EnnFICOMP i16DE26nnFISUB i16DE2EnnFISUBR i16DE36nnFIDIV i16DE3EnnFIDIVR i16
DE07FIADD i16DE0FFIMUL i16DE17FICOM i16DE1FFICOMP i16DE27FISUB i16DE2FFISUBR i16DE37FIDIV i16DE3FFIDIVR i16
DE40nFIADD i16DE48nFIMUL i16DE50nFICOM i16DE58nFICOMP i16DE60nFISUB i16DE68nFISUBR i16DE70nFIDIV i16DE78nFIDIVR i16
DE41nFIADD i16DE49nFIMUL i16DE51nFICOM i16DE59nFICOMP i16DE61nFISUB i16DE69nFISUBR i16DE71nFIDIV i16DE79nFIDIVR i16
DE42nFIADD i16DE4AnFIMUL i16DE52nFICOM i16DE5AnFICOMP i16DE62nFISUB i16DE6AnFISUBR i16DE72nFIDIV i16DE7AnFIDIVR i16
DE43nFIADD i16DE4BnFIMUL i16DE53nFICOM i16DE5BnFICOMP i16DE63nFISUB i16DE6BnFISUBR i16DE73nFIDIV i16DE7BnFIDIVR i16
DE44nFIADD i16DE4CnFIMUL i16DE54nFICOM i16DE5CnFICOMP i16DE64nFISUB i16DE6CnFISUBR i16DE74nFIDIV i16DE7CnFIDIVR i16
DE45nFIADD i16DE4DnFIMUL i16DE55nFICOM i16DE5DnFICOMP i16DE65nFISUB i16DE6DnFISUBR i16DE75nFIDIV i16DE7DnFIDIVR i16
DE46nFIADD i16DE4EnFIMUL i16DE56nFICOM i16DE5EnFICOMP i16DE66nFISUB i16DE6EnFISUBR i16DE76nFIDIV i16DE7EnFIDIVR i16
DE47nFIADD i16DE4FnFIMUL i16DE57nFICOM i16DE5FnFICOMP i16DE67nFISUB i16DE6FnFISUBR i16DE77nFIDIV i16DE7FnFIDIVR i16
DE80nnFIADD i16DE88nnFIMUL i16DE90nnFICOM i16DE98nnFICOMP i16DEA0nnFISUB i16DEA8nnFISUBR i16DEB0nnFIDIV i16DEB8nnFIDIVR i16
DE81nnFIADD i16DE89nnFIMUL i16DE91nnFICOM i16DE99nnFICOMP i16DEA1nnFISUB i16DEA9nnFISUBR i16DEB1nnFIDIV i16DEB9nnFIDIVR i16
DE82nnFIADD i16DE8AnnFIMUL i16DE92nnFICOM i16DE9AnnFICOMP i16DEA2nnFISUB i16DEAAnnFISUBR i16DEB2nnFIDIV i16DEBAnnFIDIVR i16
DE83nnFIADD i16DE8BnnFIMUL i16DE93nnFICOM i16DE9BnnFICOMP i16DEA3nnFISUB i16DEABnnFISUBR i16DEB3nnFIDIV i16DEBBnnFIDIVR i16
DE84nnFIADD i16DE8CnnFIMUL i16DE94nnFICOM i16DE9CnnFICOMP i16DEA4nnFISUB i16DEACnnFISUBR i16DEB4nnFIDIV i16DEBCnnFIDIVR i16
DE85nnFIADD i16DE8DnnFIMUL i16DE95nnFICOM i16DE9DnnFICOMP i16DEA5nnFISUB i16DEADnnFISUBR i16DEB5nnFIDIV i16DEBDnnFIDIVR i16
DE86nnFIADD i16DE8EnnFIMUL i16DE96nnFICOM i16DE9EnnFICOMP i16DEA6nnFISUB i16DEAEnnFISUBR i16DEB6nnFIDIV i16DEBEnnFIDIVR i16
DE87nnFIADD i16DE8FnnFIMUL i16DE97nnFICOM i16DE9FnnFICOMP i16DEA7nnFISUB i16DEAFnnFISUBR i16DEB7nnFIDIV i16DEBFnnFIDIVR i16
DA00FIADD i32DA08FIMUL i32DA10FICOM i32DA18FICOMP i32DA20FISUB i32DA28FISUBR i32DA30FIDIV i32DA38FIDIVR i32
DA01FIADD i32DA09FIMUL i32DA11FICOM i32DA19FICOMP i32DA21FISUB i32DA29FISUBR i32DA31FIDIV i32DA39FIDIVR i32
DA02FIADD i32DA0AFIMUL i32DA12FICOM i32DA1AFICOMP i32DA22FISUB i32DA2AFISUBR i32DA32FIDIV i32DA3AFIDIVR i32
DA03FIADD i32DA0BFIMUL i32DA13FICOM i32DA1BFICOMP i32DA23FISUB i32DA2BFISUBR i32DA33FIDIV i32DA3BFIDIVR i32
DA04FIADD i32DA0CFIMUL i32DA14FICOM i32DA1CFICOMP i32DA24FISUB i32DA2CFISUBR i32DA34FIDIV i32DA3CFIDIVR i32
DA05FIADD i32DA0DFIMUL i32DA15FICOM i32DA1DFICOMP i32DA25FISUB i32DA2DFISUBR i32DA35FIDIV i32DA3DFIDIVR i32
DA06nnFIADD i32DA0EnnFIMUL i32DA16nnFICOM i32DA1EnnFICOMP i32DA26nnFISUB i32DA2EnnFISUBR i32DA36nnFIDIV i32DA3EnnFIDIVR i32
DA07FIADD i32DA0FFIMUL i32DA17FICOM i32DA1FFICOMP i32DA27FISUB i32DA2FFISUBR i32DA37FIDIV i32DA3FFIDIVR i32
DA40nFIADD i32DA48nFIMUL i32DA50nFICOM i32DA58nFICOMP i32DA60nFISUB i32DA68nFISUBR i32DA70nFIDIV i32DA78nFIDIVR i32
DA41nFIADD i32DA49nFIMUL i32DA51nFICOM i32DA59nFICOMP i32DA61nFISUB i32DA69nFISUBR i32DA71nFIDIV i32DA79nFIDIVR i32
DA42nFIADD i32DA4AnFIMUL i32DA52nFICOM i32DA5AnFICOMP i32DA62nFISUB i32DA6AnFISUBR i32DA72nFIDIV i32DA7AnFIDIVR i32
DA43nFIADD i32DA4BnFIMUL i32DA53nFICOM i32DA5BnFICOMP i32DA63nFISUB i32DA6BnFISUBR i32DA73nFIDIV i32DA7BnFIDIVR i32
DA44nFIADD i32DA4CnFIMUL i32DA54nFICOM i32DA5CnFICOMP i32DA64nFISUB i32DA6CnFISUBR i32DA74nFIDIV i32DA7CnFIDIVR i32
DA45nFIADD i32DA4DnFIMUL i32DA55nFICOM i32DA5DnFICOMP i32DA65nFISUB i32DA6DnFISUBR i32DA75nFIDIV i32DA7DnFIDIVR i32
DA46nFIADD i32DA4EnFIMUL i32DA56nFICOM i32DA5EnFICOMP i32DA66nFISUB i32DA6EnFISUBR i32DA76nFIDIV i32DA7EnFIDIVR i32
DA47nFIADD i32DA4FnFIMUL i32DA57nFICOM i32DA5FnFICOMP i32DA67nFISUB i32DA6FnFISUBR i32DA77nFIDIV i32DA7FnFIDIVR i32
DA80nnFIADD i32DA88nnFIMUL i32DA90nnFICOM i32DA98nnFICOMP i32DAA0nnFISUB i32DAA8nnFISUBR i32DAB0nnFIDIV i32DAB8nnFIDIVR i32
DA81nnFIADD i32DA89nnFIMUL i32DA91nnFICOM i32DA99nnFICOMP i32DAA1nnFISUB i32DAA9nnFISUBR i32DAB1nnFIDIV i32DAB9nnFIDIVR i32
DA82nnFIADD i32DA8AnnFIMUL i32DA92nnFICOM i32DA9AnnFICOMP i32DAA2nnFISUB i32DAAAnnFISUBR i32DAB2nnFIDIV i32DABAnnFIDIVR i32
DA83nnFIADD i32DA8BnnFIMUL i32DA93nnFICOM i32DA9BnnFICOMP i32DAA3nnFISUB i32DAABnnFISUBR i32DAB3nnFIDIV i32DABBnnFIDIVR i32
DA84nnFIADD i32DA8CnnFIMUL i32DA94nnFICOM i32DA9CnnFICOMP i32DAA4nnFISUB i32DAACnnFISUBR i32DAB4nnFIDIV i32DABCnnFIDIVR i32
DA85nnFIADD i32DA8DnnFIMUL i32DA95nnFICOM i32DA9DnnFICOMP i32DAA5nnFISUB i32DAADnnFISUBR i32DAB5nnFIDIV i32DABDnnFIDIVR i32
DA86nnFIADD i32DA8EnnFIMUL i32DA96nnFICOM i32DA9EnnFICOMP i32DAA6nnFISUB i32DAAEnnFISUBR i32DAB6nnFIDIV i32DABEnnFIDIVR i32
DA87nnFIADD i32DA8FnnFIMUL i32DA97nnFICOM i32DA9FnnFICOMP i32DAA7nnFISUB i32DAAFnnFISUBR i32DAB7nnFIDIV i32DABFnnFIDIVR i32
D8C0FADD ST,ST0D8C8FMUL ST,ST0D8D0FCOM ST0D8D8FCOMP ST0D8E0FSUB ST,ST0D8E8FSUBR ST,ST0D8F0FDIV ST,ST0D8F8FDIVR ST,ST0
D8C1FADD ST,ST1D8C9FMUL ST,ST1D8D1FCOM ST1D8D9FCOMP ST1D8E1FSUB ST,ST1D8E9FSUBR ST,ST1D8F1FDIV ST,ST1D8F9FDIVR ST,ST1
D8C2FADD ST,ST2D8CAFMUL ST,ST2D8D2FCOM ST2D8DAFCOMP ST2D8E2FSUB ST,ST2D8EAFSUBR ST,ST2D8F2FDIV ST,ST2D8FAFDIVR ST,ST2
D8C3FADD ST,ST3D8CBFMUL ST,ST3D8D3FCOM ST3D8DBFCOMP ST3D8E3FSUB ST,ST3D8EBFSUBR ST,ST3D8F3FDIV ST,ST3D8FBFDIVR ST,ST3
D8C4FADD ST,ST4D8CCFMUL ST,ST4D8D4FCOM ST4D8DCFCOMP ST4D8E4FSUB ST,ST4D8ECFSUBR ST,ST4D8F4FDIV ST,ST4D8FCFDIVR ST,ST4
D8C5FADD ST,ST5D8CDFMUL ST,ST5D8D5FCOM ST5D8DDFCOMP ST5D8E5FSUB ST,ST5D8EDFSUBR ST,ST5D8F5FDIV ST,ST5D8FDFDIVR ST,ST5
D8C6FADD ST,ST6D8CEFMUL ST,ST6D8D6FCOM ST6D8DEFCOMP ST6D8E6FSUB ST,ST6D8EEFSUBR ST,ST6D8F6FDIV ST,ST6D8FEFDIVR ST,ST6
D8C7FADD ST,ST7D8CFFMUL ST,ST7D8D7FCOM ST7D8DFFCOMP ST7D8E7FSUB ST,ST7D8EFFSUBR ST,ST7D8F7FDIV ST,ST7D8FFFDIVR ST,ST7
DCC0FADD ST0,STDCC8FMUL ST0,STDCE0FSUBR ST0,STDCE8FSUB ST0,STDCF0FDIVR ST0,STDCF8FDIV ST0,ST
DCC1FADD ST1,STDCC9FMUL ST1,STDCE1FSUBR ST1,STDCE9FSUB ST1,STDCF1FDIVR ST1,STDCF9FDIV ST1,ST
DCC2FADD ST2,STDCCAFMUL ST2,STDCE2FSUBR ST2,STDCEAFSUB ST2,STDCF2FDIVR ST2,STDCFAFDIV ST2,ST
DCC3FADD ST3,STDCCBFMUL ST3,STDCE3FSUBR ST3,STDCEBFSUB ST3,STDCF3FDIVR ST3,STDCFBFDIV ST3,ST
DCC4FADD ST4,STDCCCFMUL ST4,STDCE4FSUBR ST4,STDCECFSUB ST4,STDCF4FDIVR ST4,STDCFCFDIV ST4,ST
DCC5FADD ST5,STDCCDFMUL ST5,STDCE5FSUBR ST5,STDCEDFSUB ST5,STDCF5FDIVR ST5,STDCFDFDIV ST5,ST
DCC6FADD ST6,STDCCEFMUL ST6,STDCE6FSUBR ST6,STDCEEFSUB ST6,STDCF6FDIVR ST6,STDCFEFDIV ST6,ST
DCC7FADD ST7,STDCCFFMUL ST7,STDCE7FSUBR ST7,STDCEFFSUB ST7,STDCF7FDIVR ST7,STDCFFFDIV ST7,ST
DEC0FADDP ST0,STDEC8FMULP ST0,STDED0FCOMP ST0DEE0FSUBRP ST0,STDEE8FSUBP ST0,STDEF0FDIVRP ST0,STDEF8FDIVP ST0,ST
DEC1FADDP ST1,STDEC9FMULP ST1,STDED1FCOMP ST1DED9FCOMPP ST1DEE1FSUBRP ST1,STDEE9FSUBP ST1,STDEF1FDIVRP ST1,STDEF9FDIVP ST1,ST
DEC2FADDP ST2,STDECAFMULP ST2,STDED2FCOMP ST2DEE2FSUBRP ST2,STDEEAFSUBP ST2,STDEF2FDIVRP ST2,STDEFAFDIVP ST2,ST
DEC3FADDP ST3,STDECBFMULP ST3,STDED3FCOMP ST3DEE3FSUBRP ST3,STDEEBFSUBP ST3,STDEF3FDIVRP ST3,STDEFBFDIVP ST3,ST
DEC4FADDP ST4,STDECCFMULP ST4,STDED4FCOMP ST4DEE4FSUBRP ST4,STDEECFSUBP ST4,STDEF4FDIVRP ST4,STDEFCFDIVP ST4,ST
DEC5FADDP ST5,STDECDFMULP ST5,STDED5FCOMP ST5DEE5FSUBRP ST5,STDEEDFSUBP ST5,STDEF5FDIVRP ST5,STDEFDFDIVP ST5,ST
DEC6FADDP ST6,STDECEFMULP ST6,STDED6FCOMP ST6DEE6FSUBRP ST6,STDEEEFSUBP ST6,STDEF6FDIVRP ST6,STDEFEFDIVP ST6,ST
DEC7FADDP ST7,STDECFFMULP ST7,STDED7FCOMP ST7DEE7FSUBRP ST7,STDEEFFSUBP ST7,STDEF7FDIVRP ST7,STDEFFFDIVP ST7,ST
DAC0FCMOVB ST0DAC8FCMOVE ST0DAD0FCMOVB ST0DAD8FCMOVU ST0
DAC1FCMOVB ST1DAC9FCMOVE ST1DAD1FCMOVB ST1DAD9FCMOVU ST1DAE9FUCOMP
DAC2FCMOVB ST2DACAFCMOVE ST2DAD2FCMOVB ST2DADAFCMOVU ST2
DAC3FCMOVB ST3DACBFCMOVE ST3DAD3FCMOVB ST3DADBFCMOVU ST3
DAC4FCMOVB ST4DACCFCMOVE ST4DAD4FCMOVB ST4DADCFCMOVU ST4
DAC5FCMOVB ST5DACDFCMOVE ST5DAD5FCMOVB ST5DADDFCMOVU ST5
DAC6FCMOVB ST6DACEFCMOVE ST6DAD6FCMOVB ST6DADEFCMOVU ST6
DAC7FCMOVB ST7DACFFCMOVE ST7DAD7FCMOVB ST7DADFFCMOVU ST7
OpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemo
D900FLD f32D910FST f32D918FSTP f32D938FSTCW u16D920FLDENV envD930FSTENV envD928FLDCW u16
D901FLD f32D911FST f32D919FSTP f32D939FSTCW u16D921FLDENV envD931FSTENV envD929FLDCW u16
D902FLD f32D912FST f32D91AFSTP f32D93AFSTCW u16D922FLDENV envD932FSTENV envD92AFLDCW u16
D903FLD f32D913FST f32D91BFSTP f32D93BFSTCW u16D923FLDENV envD933FSTENV envD92BFLDCW u16
D904FLD f32D914FST f32D91CFSTP f32D93CFSTCW u16D924FLDENV envD934FSTENV envD92CFLDCW u16
D905FLD f32D915FST f32D91DFSTP f32D93DFSTCW u16D925FLDENV envD935FSTENV envD92DFLDCW u16
D906nnFLD f32D916nnFST f32D91EnnFSTP f32D93EnnFSTCW u16D926nnFLDENV envD936nnFSTENV envD92EnnFLDCW u16
D907FLD f32D917FST f32D91FFSTP f32D93FFSTCW u16D927FLDENV envD937FSTENV envD92FFLDCW u16
D940nFLD f32D950nFST f32D958nFSTP f32D978nFSTCW u16D960nFLDENV envD970nFSTENV envD968nFLDCW u16
D941nFLD f32D951nFST f32D959nFSTP f32D979nFSTCW u16D961nFLDENV envD971nFSTENV envD969nFLDCW u16
D942nFLD f32D952nFST f32D95AnFSTP f32D97AnFSTCW u16D962nFLDENV envD972nFSTENV envD96AnFLDCW u16
D943nFLD f32D953nFST f32D95BnFSTP f32D97BnFSTCW u16D963nFLDENV envD973nFSTENV envD96BnFLDCW u16
D944nFLD f32D954nFST f32D95CnFSTP f32D97CnFSTCW u16D964nFLDENV envD974nFSTENV envD96CnFLDCW u16
D945nFLD f32D955nFST f32D95DnFSTP f32D97DnFSTCW u16D965nFLDENV envD975nFSTENV envD96DnFLDCW u16
D946nFLD f32D956nFST f32D95EnFSTP f32D97EnFSTCW u16D966nFLDENV envD976nFSTENV envD96EnFLDCW u16
D947nFLD f32D957nFST f32D95FnFSTP f32D97FnFSTCW u16D967nFLDENV envD977nFSTENV envD96FnFLDCW u16
D980nnFLD f32D990nnFST f32D998nnFSTP f32D9B8nnFSTCW u16D9A0nnFLDENV envD9B0nnFSTENV envD9A8nnFLDCW u16
D981nnFLD f32D991nnFST f32D999nnFSTP f32D9B9nnFSTCW u16D9A1nnFLDENV envD9B1nnFSTENV envD9A9nnFLDCW u16
D982nnFLD f32D992nnFST f32D99AnnFSTP f32D9BAnnFSTCW u16D9A2nnFLDENV envD9B2nnFSTENV envD9AAnnFLDCW u16
D983nnFLD f32D993nnFST f32D99BnnFSTP f32D9BBnnFSTCW u16D9A3nnFLDENV envD9B3nnFSTENV envD9ABnnFLDCW u16
D984nnFLD f32D994nnFST f32D99CnnFSTP f32D9BCnnFSTCW u16D9A4nnFLDENV envD9B4nnFSTENV envD9ACnnFLDCW u16
D985nnFLD f32D995nnFST f32D99DnnFSTP f32D9BDnnFSTCW u16D9A5nnFLDENV envD9B5nnFSTENV envD9ADnnFLDCW u16
D986nnFLD f32D996nnFST f32D99EnnFSTP f32D9BEnnFSTCW u16D9A6nnFLDENV envD9B6nnFSTENV envD9AEnnFLDCW u16
D987nnFLD f32D997nnFST f32D99FnnFSTP f32D9BFnnFSTCW u16D9A7nnFLDENV envD9B7nnFSTENV envD9AFnnFLDCW u16
DD00FLD f64DD10FST f64DD18FSTP f64DD38FSTSW u16DD20FRSTOR sttDD30FSAVE stt
DD01FLD f64DD11FST f64DD19FSTP f64DD39FSTSW u16DD21FRSTOR sttDD31FSAVE stt
DD02FLD f64DD12FST f64DD1AFSTP f64DD3AFSTSW u16DD22FRSTOR sttDD32FSAVE stt
DD03FLD f64DD13FST f64DD1BFSTP f64DD3BFSTSW u16DD23FRSTOR sttDD33FSAVE stt
DD04FLD f64DD14FST f64DD1CFSTP f64DD3CFSTSW u16DD24FRSTOR sttDD34FSAVE stt
DD05FLD f64DD15FST f64DD1DFSTP f64DD3DFSTSW u16DD25FRSTOR sttDD35FSAVE stt
DD06nnFLD f64DD16nnFST f64DD1EnnFSTP f64DD3EnnFSTSW u16DD26nnFRSTOR sttDD36nnFSAVE stt
DD07FLD f64DD17FST f64DD1FFSTP f64DD3FFSTSW u16DD27FRSTOR sttDD37FSAVE stt
DD40nFLD f64DD50nFST f64DD58nFSTP f64DD78nFSTSW u16DD60nFRSTOR sttDD70nFSAVE stt
DD41nFLD f64DD51nFST f64DD59nFSTP f64DD79nFSTSW u16DD61nFRSTOR sttDD71nFSAVE stt
DD42nFLD f64DD52nFST f64DD5AnFSTP f64DD7AnFSTSW u16DD62nFRSTOR sttDD72nFSAVE stt
DD43nFLD f64DD53nFST f64DD5BnFSTP f64DD7BnFSTSW u16DD63nFRSTOR sttDD73nFSAVE stt
DD44nFLD f64DD54nFST f64DD5CnFSTP f64DD7CnFSTSW u16DD64nFRSTOR sttDD74nFSAVE stt
DD45nFLD f64DD55nFST f64DD5DnFSTP f64DD7DnFSTSW u16DD65nFRSTOR sttDD75nFSAVE stt
DD46nFLD f64DD56nFST f64DD5EnFSTP f64DD7EnFSTSW u16DD66nFRSTOR sttDD76nFSAVE stt
DD47nFLD f64DD57nFST f64DD5FnFSTP f64DD7FnFSTSW u16DD67nFRSTOR sttDD77nFSAVE stt
DD80nnFLD f64DD90nnFST f64DD98nnFSTP f64DDB8nnFSTSW u16DDA0nnFRSTOR sttDDB0nnFSAVE stt
DD81nnFLD f64DD91nnFST f64DD99nnFSTP f64DDB9nnFSTSW u16DDA1nnFRSTOR sttDDB1nnFSAVE stt
DD82nnFLD f64DD92nnFST f64DD9AnnFSTP f64DDBAnnFSTSW u16DDA2nnFRSTOR sttDDB2nnFSAVE stt
DD83nnFLD f64DD93nnFST f64DD9BnnFSTP f64DDBBnnFSTSW u16DDA3nnFRSTOR sttDDB3nnFSAVE stt
DD84nnFLD f64DD94nnFST f64DD9CnnFSTP f64DDBCnnFSTSW u16DDA4nnFRSTOR sttDDB4nnFSAVE stt
DD85nnFLD f64DD95nnFST f64DD9DnnFSTP f64DDBDnnFSTSW u16DDA5nnFRSTOR sttDDB5nnFSAVE stt
DD86nnFLD f64DD96nnFST f64DD9EnnFSTP f64DDBEnnFSTSW u16DDA6nnFRSTOR sttDDB6nnFSAVE stt
DD87nnFLD f64DD97nnFST f64DD9FnnFSTP f64DDBFnnFSTSW u16DDA7nnFRSTOR sttDDB7nnFSAVE stt
DF00FILD i16DF10FIST i16DF18FISTP i16DF38FISTP i64DF20FBLD bcdDF30FBSTP bcdDF28FILD i64
DF01FILD i16DF11FIST i16DF19FISTP i16DF39FISTP i64DF21FBLD bcdDF31FBSTP bcdDF29FILD i64
DF02FILD i16DF12FIST i16DF1AFISTP i16DF3AFISTP i64DF22FBLD bcdDF32FBSTP bcdDF2AFILD i64
DF03FILD i16DF13FIST i16DF1BFISTP i16DF3BFISTP i64DF23FBLD bcdDF33FBSTP bcdDF2BFILD i64
DF04FILD i16DF14FIST i16DF1CFISTP i16DF3CFISTP i64DF24FBLD bcdDF34FBSTP bcdDF2CFILD i64
DF05FILD i16DF15FIST i16DF1DFISTP i16DF3DFISTP i64DF25FBLD bcdDF35FBSTP bcdDF2DFILD i64
DF06nnFILD i16DF16nnFIST i16DF1EnnFISTP i16DF3EnnFISTP i64DF26nnFBLD bcdDF36nnFBSTP bcdDF2EnnFILD i64
DF07FILD i16DF17FIST i16DF1FFISTP i16DF3FFISTP i64DF27FBLD bcdDF37FBSTP bcdDF2FFILD i64
DF40nFILD i16DF50nFIST i16DF58nFISTP i16DF78nFISTP i64DF60nFBLD bcdDF70nFBSTP bcdDF68nFILD i64
DF41nFILD i16DF51nFIST i16DF59nFISTP i16DF79nFISTP i64DF61nFBLD bcdDF71nFBSTP bcdDF69nFILD i64
DF42nFILD i16DF52nFIST i16DF5AnFISTP i16DF7AnFISTP i64DF62nFBLD bcdDF72nFBSTP bcdDF6AnFILD i64
DF43nFILD i16DF53nFIST i16DF5BnFISTP i16DF7BnFISTP i64DF63nFBLD bcdDF73nFBSTP bcdDF6BnFILD i64
DF44nFILD i16DF54nFIST i16DF5CnFISTP i16DF7CnFISTP i64DF64nFBLD bcdDF74nFBSTP bcdDF6CnFILD i64
DF45nFILD i16DF55nFIST i16DF5DnFISTP i16DF7DnFISTP i64DF65nFBLD bcdDF75nFBSTP bcdDF6DnFILD i64
DF46nFILD i16DF56nFIST i16DF5EnFISTP i16DF7EnFISTP i64DF66nFBLD bcdDF76nFBSTP bcdDF6EnFILD i64
DF47nFILD i16DF57nFIST i16DF5FnFISTP i16DF7FnFISTP i64DF67nFBLD bcdDF77nFBSTP bcdDF6FnFILD i64
DF80nnFILD i16DF90nnFIST i16DF98nnFISTP i16DFB8nnFISTP i64DFA0nnFBLD bcdDFB0nnFBSTP bcdDFA8nnFILD i64
DF81nnFILD i16DF91nnFIST i16DF99nnFISTP i16DFB9nnFISTP i64DFA1nnFBLD bcdDFB1nnFBSTP bcdDFA9nnFILD i64
DF82nnFILD i16DF92nnFIST i16DF9AnnFISTP i16DFBAnnFISTP i64DFA2nnFBLD bcdDFB2nnFBSTP bcdDFAAnnFILD i64
DF83nnFILD i16DF93nnFIST i16DF9BnnFISTP i16DFBBnnFISTP i64DFA3nnFBLD bcdDFB3nnFBSTP bcdDFABnnFILD i64
DF84nnFILD i16DF94nnFIST i16DF9CnnFISTP i16DFBCnnFISTP i64DFA4nnFBLD bcdDFB4nnFBSTP bcdDFACnnFILD i64
DF85nnFILD i16DF95nnFIST i16DF9DnnFISTP i16DFBDnnFISTP i64DFA5nnFBLD bcdDFB5nnFBSTP bcdDFADnnFILD i64
DF86nnFILD i16DF96nnFIST i16DF9EnnFISTP i16DFBEnnFISTP i64DFA6nnFBLD bcdDFB6nnFBSTP bcdDFAEnnFILD i64
DF87nnFILD i16DF97nnFIST i16DF9FnnFISTP i16DFBFnnFISTP i64DFA7nnFBLD bcdDFB7nnFBSTP bcdDFAFnnFILD i64
DB00FILD i32DB10FIST i32DB18FISTP i32DB38FSTP f80DB28FLD f80
DB01FILD i32DB11FIST i32DB19FISTP i32DB39FSTP f80DB29FLD f80
DB02FILD i32DB12FIST i32DB1AFISTP i32DB3AFSTP f80DB2AFLD f80
DB03FILD i32DB13FIST i32DB1BFISTP i32DB3BFSTP f80DB2BFLD f80
DB04FILD i32DB14FIST i32DB1CFISTP i32DB3CFSTP f80DB2CFLD f80
DB05FILD i32DB15FIST i32DB1DFISTP i32DB3DFSTP f80DB2DFLD f80
DB06nnFILD i32DB16nnFIST i32DB1EnnFISTP i32DB3EnnFSTP f80DB2EnnFLD f80
DB07FILD i32DB17FIST i32DB1FFISTP i32DB3FFSTP f80DB2FFLD f80
DB40nFILD i32DB50nFIST i32DB58nFISTP i32DB78nFSTP f80DB68nFLD f80
DB41nFILD i32DB51nFIST i32DB59nFISTP i32DB79nFSTP f80DB69nFLD f80
DB42nFILD i32DB52nFIST i32DB5AnFISTP i32DB7AnFSTP f80DB6AnFLD f80
DB43nFILD i32DB53nFIST i32DB5BnFISTP i32DB7BnFSTP f80DB6BnFLD f80
DB44nFILD i32DB54nFIST i32DB5CnFISTP i32DB7CnFSTP f80DB6CnFLD f80
DB45nFILD i32DB55nFIST i32DB5DnFISTP i32DB7DnFSTP f80DB6DnFLD f80
DB46nFILD i32DB56nFIST i32DB5EnFISTP i32DB7EnFSTP f80DB6EnFLD f80
DB47nFILD i32DB57nFIST i32DB5FnFISTP i32DB7FnFSTP f80DB6FnFLD f80
DB80nnFILD i32DB90nnFIST i32DB98nnFISTP i32DBB8nnFSTP f80DBA8nnFLD f80
DB81nnFILD i32DB91nnFIST i32DB99nnFISTP i32DBB9nnFSTP f80DBA9nnFLD f80
DB82nnFILD i32DB92nnFIST i32DB9AnnFISTP i32DBBAnnFSTP f80DBAAnnFLD f80
DB83nnFILD i32DB93nnFIST i32DB9BnnFISTP i32DBBBnnFSTP f80DBABnnFLD f80
DB84nnFILD i32DB94nnFIST i32DB9CnnFISTP i32DBBCnnFSTP f80DBACnnFLD f80
DB85nnFILD i32DB95nnFIST i32DB9DnnFISTP i32DBBDnnFSTP f80DBADnnFLD f80
DB86nnFILD i32DB96nnFIST i32DB9EnnFISTP i32DBBEnnFSTP f80DBAEnnFLD f80
DB87nnFILD i32DB97nnFIST i32DB9FnnFISTP i32DBBFnnFSTP f80DBAFnnFLD f80
D9C0FLD ST0D9F8FPREMD9E0FCHSD9F0F2XM1D9E8FLD1D9C8FXCH ST0
D9C1FLD ST1D9F9FYL2XPD9E1FABSD9F1FYL2XD9E9FLDL2TD9C9FXCH ST1
D9C2FLD ST2D9FAFSQRTD9F2FPTAND9EAFLDL2ED9CAFXCH ST2
D9C3FLD ST3D9FBFSINCOD9F3FPATAND9EBFLDPID9CBFXCH ST3
D9C4FLD ST4D9FCFRNDIND9E4FTSTD9F4FXTRACD9ECFLDLG2D9CCFXCH ST4
D9C5FLD ST5D9FDFSCALED9E5FXAMD9F5FPREM1D9EDFLDLN2D9CDFXCH ST5
D9C6FLD ST6D9FEFSIND9F6FDECSTD9EEFLDZD9CEFXCH ST6
D9C7FLD ST7D9FFFCOSD9F7FINCSTD9CFFXCH ST7
DDC0FFREE ST0DDD0FST ST0DDD8FSTP ST0DDE0FCOM ST0DDE8FCOMP ST0
DDC1FFREE ST1DDD1FST ST1DDD9FSTP ST1DDE1FCOM ST1DDE9FCOMP ST1
DDC2FFREE ST2DDD2FST ST2DDDAFSTP ST2DDE2FCOM ST2DDEAFCOMP ST2
DDC3FFREE ST3DDD3FST ST3DDDBFSTP ST3DDE3FCOM ST3DDEBFCOMP ST3
DDC4FFREE ST4DDD4FST ST4DDDCFSTP ST4DDE4FCOM ST4DDECFCOMP ST4
DDC5FFREE ST5DDD5FST ST5DDDDFSTP ST5DDE5FCOM ST5DDEDFCOMP ST5
DDC6FFREE ST6DDD6FST ST6DDDEFSTP ST6DDE6FCOM ST6DDEEFCOMP ST6
DDC7FFREE ST7DDD7FST ST7DDDFFSTP ST7DDE7FCOM ST7DDEFFCOMP ST7
DFC0FFREEP ST0DFE0FSTSW AXDFF0FCOMIP ST0
DFC1FFREEP ST1DFF1FCOMIP ST1
DFC2FFREEP ST2DFF2FCOMIP ST2
DFC3FFREEP ST3DFF3FCOMIP ST3
DFC4FFREEP ST4DFF4FCOMIP ST4
DFC5FFREEP ST5DFF5FCOMIP ST5
DFC6FFREEP ST6DFF6FCOMIP ST6
DFC7FFREEP ST7DFF7FCOMIP ST7
DBC0FCMOVN ST0DBD0FCMOVN ST0DBD8FCMOVN ST0DBE0FENIDBF0FCOMI ST0DBC8FCMOVN ST0
DBC1FCMOVN ST1DBD1FCMOVN ST1DBD9FCMOVN ST1DBE1FDISIDBF1FCOMI ST1DBC9FCMOVN ST1
DBC2FCMOVN ST2DBD2FCMOVN ST2DBDAFCMOVN ST2DBE2FCLEXDBF2FCOMI ST2DBCAFCMOVN ST2
DBC3FCMOVN ST3DBD3FCMOVN ST3DBDBFCMOVN ST3DBE3FINITDBF3FCOMI ST3DBCBFCMOVN ST3
DBC4FCMOVN ST4DBD4FCMOVN ST4DBDCFCMOVN ST4DBE4FSETPMDBF4FCOMI ST4DBCCFCMOVN ST4
DBC5FCMOVN ST5DBD5FCMOVN ST5DBDDFCMOVN ST5DBF5FCOMI ST5DBCDFCMOVN ST5
DBC6FCMOVN ST6DBD6FCMOVN ST6DBDEFCMOVN ST6DBF6FCOMI ST6DBCEFCMOVN ST6
DBC7FCMOVN ST7DBD7FCMOVN ST7DBDFFCMOVN ST7DBF7FCOMI ST7DBCFFCMOVN ST7
OpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemoOpcodeMnemo