High-level synthesis

High-level synthesis, sometimes referred to as C synthesis, electronic system-level synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer level design in a hardware description language, which is in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.
Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level, and algorithmic level.
While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. The implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

History

Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the finite-state machine. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path.
First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler and used Verilog or VHDL as input languages. The abstraction level used was partially timed processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.
In 2004, there emerged a number of next generation commercial high-level synthesis products which provided synthesis of circuits specified at C level to a register transfer level specification. Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.
High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.

Lexical processing
Algorithm optimization
Control/Dataflow analysis
Library processing
Resource allocation
Scheduling
Functional unit binding
Register binding
Output processing
Input Rebundling
Functionality

In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency.

Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis. These constraints can be broken into

Hierarchy
Interface
Memory
Loop
Low-level timing constraints
iteration
Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.

Vendors

Data reported on recent Survey

Status	Compiler	Owner	License	Input	Output	Year	Domain	Test Bench	FP	FixP
In Use		TIMA Lab.	Academic	C subset	VHDL	2012	All	Yes	No	No
In Use		Y Explorations	Commercial	C	VHDL/Verilog	2001	All	Yes	No	Yes
In Use		PoliMi	Academic	C	VHDL/Verilog	2012	All	Yes	Yes	No
In Use	Bluespec	BlueSpec Inc.	Commercial	BSV	SystemVerilog	2007	All	No	No	No
In Use	CHC	Altium	Commercial	C subset	VHDL/Verilog	2008	All	No	Yes	Yes
In Use	CoDeveloper	Impulse Accelerated	Commercial	Impulse-C	VHDL	2003	Image Streaming	Yes	Yes	No
In Use		MathWorks	Commercial	MATLAB, Simulink, Stateflow, Simscape	VHDL / Verilog	2003	Control Systems, Signal Processing, Wireless, Radar, Communications, Image and Computer Vision	Yes	Yes	Yes
In Use	Stratus	Cadence	Commercial	C/C++ SystemC	RTL	2015	All	Yes	No	Yes
In Use	CyberWorkbench	NEC	Commercial	BDL, SystemC	VHDL/Verilog	2011	All	Cycle/ Formal	Yes	Yes
In Use	Catapult	Mentor	Commercial	C, C++, SystemC	VHDL/Verilog	2004	Streaming	No	No	Yes
In Use	DWARV	TU. Delft	Academic	C subset	VHDL	2012	All	Yes	Yes	Yes
In Use		U. Bretagne	Academic	C/C++	VHDL	2010	DSP	Yes	No	Yes
In Use		Lombiq Technologies	Commercial	C#/C++/F#...	VHDL	2015	.NET	Yes	Yes	Yes
In Use		FPGA Cores	Commercial	C/C++	VHDL/Verilog	2019	All	Yes	No	No
In Use		Intel FPGA	Commercial	C/C++	Verilog	2017	All	Yes	Yes	Yes
In Use		LegUp Computing	Commercial	C/C++	Verilog	2017	All	Yes	Yes	Yes
In Use		U. Toronto	Academic	C	Verilog	2011	All	Yes	Yes	No
In Use	MaxCompiler	Maxeler	Commercial	MaxJ	RTL	2010	DataFlow	No	Yes	No
In Use		Jacquard Comp.	Commercial	C subset	VHDL	2010	Streaming	No	Yes	No
In Use	Symphony C	Synopsys	Commercial	C/C++	VHDL/Verilog/ SystemC	2010	All	Yes	No	Yes
In Use		Xilinx	Commercial	C/C++/SystemC	VHDL/Verilog/ SystemC	2013	All	Yes	Yes	Yes
In Use		U. Cambridge	Academic	C#	Verilog	2008	.NET	No	Yes	Yes
In Use	CHiMPS	U. Washington	Academic	C	VHDL	2008	All	No	No	No
In Use	gcc2verilog	U. Korea	Academic	C	Verilog	2011	All	No	No	No
In Use		Ajax Compilers	Commercial	C/NAC	VHDL	2012	All	Yes	Yes	Yes
In Use		U. Illinois	Academic	C	Verilog	2013	All	Yes	?	?
In Use	Trident	Los Alamos NL	Academic	C subset	VHDL	2007	Scientific	No	Yes	No
Aban- doned	AccelDSP	Xilinx	Commercial	MATLAB	VHDL/Verilog	2006	DSP	Yes	Yes	Yes
Aban- doned	C2H	Altera	Commercial	C	VHDL/Verilog	2006	All	No	No	No
Aban- doned	CtoVerilog	U. Haifa	Academic	C	Verilog	2008	All	No	No	No
Aban- doned	DEFACTO	U. South Cailf.	Academic	C	RTL	1999	DSE	No	No	No
Aban- doned	Garp	U. Berkeley	Academic	C subset	bitstream	2000	Loop	No	No	No
Aban- doned	MATCH	U. Northwest	Academic	MATLAB	VHDL	2000	Image	No	No	No
Aban- doned	Napa-C	Sarnoff Corp.	Academic	C subset	VHDL/Verilog	1998	Loop	No	No	No
Aban- doned	PipeRench	U.Carnegie M.	Academic	DIL	bistream	2000	Stream	No	No	No
Aban- doned	SA-C	U. Colorado	Academic	SA-C	VHDL	2003	Image	No	No	No
Aban- doned	SeaCucumber	U. Brigham Y.	Academic	Java	EDIF	2002	All	No	Yes	Yes
Aban- doned	SPARK	U. Cal. Irvine	Academic	C	VHDL	2003	Control	No	No	No

MATLAB HDL Coder from Mathworks
HLS-QSP from CircuitSutra Technologies
C-to-Silicon from Cadence Design Systems
Concurrent Acceleration from Concurrent EDA
Symphony C Compiler from Synopsys
QuickPlay from PLDA
PowerOpt from ChipVision
Cynthesizer from Forte Design Systems, acquired by Cadence Design Systems on 2014, February 14
Catapult C from Calypto Design Systems, part of Mentor Graphics as of 2015, September 16
CyberWorkBench from NEC
Mega Hardware
C2R from CebaTech
CoDeveloper from Impulse Accelerated Technologies
HercuLeS by Nikolaos Kavvadias
PICO from Synfora, acquired by Synopsys in June 2010
xPilot from University of California, Los Angeles
Vsyn from vsyn.ru
ngDesign from SynFlow

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High-level synthesis

History

Process stages

Functionality

Architectural constraints

Interface synthesis

Vendors