WDC 65C02


The Western Design Center 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502. The 65C02 fixed several problems in the original 6502 and added some new instructions. However, its main feature was greatly lowered power usage, on the order of 10 to 20 times less than the NMOS 6502 running at the same speed. The reduced power consumption made the 65C02 useful in portable computer roles and microcontroller systems in industrial settings. It has been used in some home computers, as well as in embedded applications, including medical-grade implanted devices.
Development began in 1981 and samples were released in early 1983. WDC licensed the design to Synertek, NCR, GTE, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.

Introduction and features

The 65C02 is a low cost, general-purpose 8-bit microprocessor with a 16-bit program counter and address bus. The register set is small, with a single 8-bit accumulator, two 8-bit index registers, an 8-bit status register, and a 16-bit program counter. In addition to the single accumulator, the first 256 bytes of RAM, the "zero page", allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The stack lies in the next 256 bytes, page one, and cannot be moved or extended. The stack grows downwards with the stack pointer starting at $01FF and decrementing as the stack grows. It has a variable-length instruction set, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and can be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip designs.
A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit or a field-programmable gate array. As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator and a software development system.
The W65C02S-14 is the production version, and is available in PDIP, PLCC and QFP packages. The maximum officially supported Ø2 clock speed is 14 MHz when operated at 5 volts, indicated by the -14 part number suffix. The "S" designation indicates that the part has a fully static core, a feature that allows Ø2 to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents if they are not continuously clocked at a rate between some minimum and maximum specified values.

General logic features

Logic features

The W65C02S may be operated at any convenient supply voltage between 1.8 and 5 volts. The data sheet AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it.
The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz, 14.31818 MHz, 14.75 MHz, 14.7456, etc., as long as VDD is sufficient to support the frequency. Designer Bill Mensch has pointed out that FMAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise FMAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of printed circuit board space.
WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.

Comparison with the NMOS 6502

Basic architecture

Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses, as well as use of fewer instructions to accomplish a given task.

Undocumented instructions removed

The original 6502 had 56 instructions, which, when combined with different addressing modes, produced a total of 151 opcodes of the possible 256 8-bit patterns. The remaining 105 unused opcodes were undefined, with the set of codes with low-order 4-bits with 3, 7, B or F left entirely unused, the 2 having only a single opcode.
The 6502 was famous for the way that some of these leftover codes actually performed actions. Due to the way the 6502's instruction decoder worked, simply setting certain bits in the opcode would cause parts of the instruction processing to take place. Some of these opcodes would immediately crash the processor, while other performed useful functions and were even given unofficial assembler mnemonics by users.
The 65C02 added a number of new opcodes that used up a number of these previously "undocumented instruction" slots, for instance, $FF was now used for the new BBS instruction. Those that remained truly unused were set to perform NOPs. Programs that took advantage of these codes will not work on the 65C02, but these codes were always documented as non-operational and should not have been used.

Bug fixes

The original 6502 had several errata when initially launched. Early versions of the processor had a defective ROR instruction, which issue MOS Technology addressed by not documenting the instruction. ROR was fixed very early in the production run and was not an issue for the vast majority of machines using the processor.
In contrast, a notorious bug that is present in all NMOS variants of the 6502 involves the jump instruction when using indirect addressing. In this addressing mode, the target address of the JMP instruction is fetched from memory, rather than being an operand to the JMP instruction. For example, JMP would fetch the value in memory locations $1234 and $1235 and load those values into the program counter, which would then cause the processor to continue execution at the address stored in the jump vector.
The bug appears when the vector address ends in $FF, which is the boundary of a memory page. In this case, JMP will fetch the most significant byte of the target address from $00 of the original page rather than $00 of the new page. Hence JMP would get the least significant byte of the target address at $12FF and the most significant byte of the target address from $1200 rather than $1300. The 65C02 corrected this issue.
More of an oversight than a bug, the state of the ecimal flag in the NMOS 6502's status register is undefined after a reset or interrupt. This means programmers have to set the flag to a known value in order to avoid any bugs related to arithmetic operations. As a result, one finds a CLD instruction in almost all 6502 interrupt handlers, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode.
During decimal mode arithmetic, the NMOS 6502 will update the egative, oerflow and ero flags to reflect the result of binary arithmetic, that is, the flags are reflecting a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction.
When executing a read-modify-write instruction, such as INC addr, all NMOS variants will do a double write on addr, first rewriting the current value found at addr and then writing the modified value. This behavior can result in difficult-to-resolve bugs if addr is a hardware register. The 65C02 instead performs a double read of addr, followed by a single write.
When performing indexed addressing, if indexing crosses a page bounday all NMOS variants will read from an invalid address before accessing the correct address. As with an R-M-W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary. With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X will do a dummy read on $1200 prior to the value of X being added to $1200. Again, if indexing on hardware register addresses, this bug can result in undefined behavior.
If an NMOS 6502 is fetching a BRK opcode at the same time a hardware interrupt occurs BRK will be ignored as the processor reacts to the interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK.

New addressing modes

The 6502 has two indirect addressing modes which dereference through 16-bit addresses stored in page zero:
A downside of this model is that if indexing is not needed, one of the index registers must still be set to zero and used in one of these instructions. The 65C02 added a non-indexed indirect addressing mode LDA to all instructions that used indexed indirect and indirect indexed modes, freeing up the index registers.
The 6502's instruction had a unique addressing mode known as "absolute indirect" that read a 16-bit value from a given memory address and then jumped to the address in that 16-bit value. For instance, if memory location $A000 holds $34 and $A001 holds $12, JMP would read those two bytes, construct the value $1234, and then jump to that location.
One common use for indirect addressing is to build branch tables, a list of entry points for subroutines that can be accessed using an index. For instance, a device driver might list the entry points for,,, etc in a table at $A000. To access the function, one would use something similar to JMP , as it is the 3rd entry in the table and each entry is 16-bits. If the driver is updated and the subroutine code moves in memory, any existing code will still work as long as it uses the table to look them up.
The 65C02 added the new "indexed absolute indirect" mode which eased the use of branch tables. This mode added the value of the X register to the absolute address and took the 16-bit address from the resulting location. For instance, to access the function from the table above, one would store 4 in X, then JMP . This style of access makes accessing branch tables simpler as a single base address is used in conjunction with an 8-bit offset.

New and modified instructions

In addition to the new addressing modes, the "base model" 65C02 also added a set of new instructions.
Both WDC and Rockwell contributed improvements to the bit testing and manipulation functions in the 65C02. WDC added new addressing modes to the BIT instruction that was present in the 6502, as well two new instructions for convenient manipulation of bit fields, a common activity in device drivers.
BIT in the 65C02 adds immediate mode, zero page indexed by X and absolute indexed by X addressing. Immediate mode addressing is particularly convenient in that it is completely non-destructive. For example:


may be used in place of:


The former preserves the value loaded from so more than one test can be performed on it. The latter sequence is destructive to the register value.
In addition to the enhancements of the BIT instruction, WDC added two instructions designed to conveniently manipulate bit fields:
Rockwell's changes added more bit manipulation instructions for directly setting and testing any bit, and combining the test, clear and branch into a single opcode. The new instructions were available from the start in Rockwell's R65C00 family, but was not part of the original 65C02 specification and not found in versions made by WDC or its other licensees. These were later copied back into the baseline design, and were available in later WDC versions.
Rockwell-specific instructions are:
In addition to the new commands above, WDC also added the STP and WAI instructions for supporting low-power modes.
, STop the Processor, halted all processing until a hardware reset was issued. This could be used to put a system to "sleep" and then rapidly wake it with a reset. However, this required some external system to maintain memory, and it was not widely used.
t had a similar effect, entering low-power mode, but this instruction woke the processor up again on the reception of an interrupt. Previously, handling an interrupt generally involved running a loop to check if an interrupt has been received, sometimes known as "spinning", checking the type when one is received, and then jumping to the processing code. This meant the processor was running during the entire process.
In contrast, in the 65C02, interrupt code could be written by having a followed immediately by a or to the handler. When the was encountered, processing stopped and the processor went into low-power mode. When the interrupt was received, it immediately processed the and handled the request.
This had the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends one cycle to save its location. With, the processor enters the low-power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction, and the processor can safely continue without spending a cycle saving state.

65SC02

The 65SC02 is a variant of the WDC 65C02 without bit instructions.

Notable uses of the 65C02

Home computers