W. Wesley Peterson
William Wesley Peterson was an American mathematician and computer scientist. He was best known for designing the cyclic redundancy check, for which research he was awarded the Japan Prize in 1999.
Peterson was born on April 22, 1924 in Muskegon, Michigan and earned his Ph.D. in 1954 from the University of Michigan. Peterson was a professor of Information and Computer Sciences at the University of Hawaii at Manoa, joining the faculty in 1964. He started work at IBM in 1954. He authored the publication of algebraic coding theory Error Correcting Codes in 1961. He co-authored a number of books on the topic of error correcting codes, including the revised 2nd edition of Error Correcting Codes. In the early 1950s he contributed significantly to the development of signal detection theory through participation in the IRE Professional Group on Information Theory. He has also done research and published in the fields of programming languages, systems programming, and networks. As well as the Japan Prize in 1999, he was awarded the Claude E. Shannon Award in 1981, and the IEEE Centennial Medal in 1984. In 2007, two years before Peterson's death, Intel added crc32 to the SSE4.2 instruction set of the x86-64 architecture.
Peterson finished 16th in the 2005 Honolulu Marathon for males ages 80 to 84. He died on May 6, 2009 in Honolulu, Hawaii survived by five children from two different marriages, his wife, and several grandchildren.
