TI MSP430


The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a CPU, the MSP430 is designed for low cost and, specifically, low power consumption embedded applications.

Applications

The MSP430 can be used for low powered embedded devices. The current drawn in idle mode can be less than 1 µA. The top CPU speed is 25 MHz. It can be throttled back for lower power consumption. The MSP430 also uses six different low-power modes, which can disable unneeded clocks and CPU. Additionally, the MSP430 is capable of wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption.
The device comes in a variety of configurations featuring the usual peripherals: internal oscillator, timer including PWM, watchdog, USART, SPI, I²C, 10/12/14/16/24-bit ADCs, and brownout reset circuitry. Some less usual peripheral options include comparators, on-chip op-amps for signal conditioning, 12-bit DAC, LCD driver, hardware multiplier, USB, and DMA for ADC results. Apart from some older EPROM and high volume mask ROM versions, all of the devices are in-system programmable via JTAG or a built in bootstrap loader using UART such as RS232, or USB on devices with USB support.
There are, however, limitations that preclude its use in more complex embedded systems. The MSP430 does not have an external memory bus, so it is limited to on-chip memory which may be too small for applications that require large buffers or data tables. Also, although it has a DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe.

MSP430 part numbering

An MSP430 part number such as "MSP430F2618ATZQWT-EP" consists of the following pieces:


Trailing suffix letters indicate options not visible to software:
There are six general generations of MSP430 processors. In order of development, they are the '3xx generation, the '1xx generation, the '4xx generation, the '2xx generation, the '5xx generation, and the '6xx generation. The digit after the generation identifies the model, the third digit identifies the amount of memory on board, and the fourth, if present, identifies a minor model variant. The most common variation is a different on-chip analog-to-digital converter.
The 3xx and 1xx generations are limited to a 16-bit address space. In the later generations this was expanded to include '430X' instructions that allow a 20-bit address space. As happened with other processor architectures, extending the addressing range beyond the 16-bit word size introduced some peculiarities and inefficiencies for programs larger than 64 kBytes.
In the following list, it helps to think of the typical 200 mA·Hr capacity of a CR2032 lithium coin cell as 200,000 μA·Hr, or 22.8 μA·year. Thus, considering only the CPU draw, such a battery could supply a 0.7 μA current draw for 32 years.
The significance of the 'RAM retention' vs the 'real-time clock mode' is that in real time clock mode the CPU can go to sleep with a clock running which will wake it up at a specific future time. In RAM retention mode, some external signal is required to wake it, e.g. I/O pin signal or SPI slave receive interrupt.

MSP430x1xx series

The is the basic generation without an embedded LCD controller. They are generally smaller than the '3xx generation. These flash- or ROM-based ultra-low-power MCUs offer 8 MIPS, 1.8–3.6 V operation, up to 60 KB flash, and a wide range of analog and digital peripherals.

MSP430F2xx series

The are similar to the '1xx generation, but operate at even lower power, support up to 16 MHz operation, and have a more accurate on-chip clock that makes it easier to operate without an external crystal. These flash-based ultra-low power devices offer 1.8–3.6 V operation. Includes the very-low power oscillator, internal pull-up/pull-down resistors, and low-pin count options.

MSP430G2xx series

The MSP430G2xx Value Series features flash-based Ultra-Low Power MCUs up to 16 MIPS with 1.8–3.6 V operation. Includes the Very-Low power Oscillator, internal pull-up/pull-down resistors, and low-pin count options, at lower prices than the MSP430F2xx series.

MSP430x3xx series

The is the oldest generation, designed for portable instrumentation with an embedded LCD controller. This also includes a frequency-locked loop oscillator that can automatically synchronize to a low-speed crystal. This generation does not support EEPROM memory, only mask ROM and UV-eraseable and one-time programmable EPROM. Later generations provide only flash memory and mask ROM options. These devices offer 2.5–5.5 V operation, up to 32 KB ROM.

MSP430x4xx series

The are similar to the '3xx generation, but include an integrated LCD controller, and are larger and more capable. These flash or ROM based devices offers 8–16 MIPS at 1.8–3.6 V operation, with FLL, and SVS. Ideal for low power metering and medical applications.

MSP430x5xx series

The are able to run up to 25 MHz, have up to 512 KB flash memory and up to 66 KB RAM. This flash-based family features low active power consumption with up to 25 MIPS at 1.8–3.6 V operation. Includes an innovative power management module for optimal power consumption and integrated USB.

MSP430x6xx series

The are able to run up to 25 MHz, have up to 512 KB flash memory and up to 66 KB RAM. This flash-based family features low active power consumption with up to 25 MIPS at 1.8–3.6 V operation. Includes an innovative power management module for optimal power consumption and integrated USB.

RF SoC (CC430) series

The provides tight integration between the microcontroller core, peripherals, software, and RF transceiver. Features <1 GHz RF transceiver, with 1.8 V–3.6 V operation. Programming using Arduino IDE is possible via the .

FRAM series

The from Texas Instruments provides unified memory with dynamic partitioning and memory access speeds 100 times faster than flash. FRAM is also capable of zero power state retention in all power modes, which means that writes are guaranteed, even in the event of a power loss. With a write endurance of over 100 trillion cycles, EEPROM is no longer required. Active power consumption at less than 100μA/MHz.

Low voltage series

The include the MSP430C09x and MSP430L092 parts. These 2 series of low voltage 16 bit microcontrollers have configurations with two 16-bit timers, an 8-bit analog-to-digital converter, an 8-bit digital-to-analog converter, and up to 11 I/O pins.

Other MSP430 families

Additional families within MSP430 include , , and parts.
:
The MSP430BQ1010 16-bit microcontroller is an advanced fixed-function device that forms the control and communications unit on the receiver side for wireless power transfer in portable applications. MSP430BQ1010 complies with the Wireless Power Consortium specification. For more information, see .
:
Automotive MSP430 microcontrollers from Texas Instruments are 16-bit, RISC-based, mixed-signal processors that are AEC-Q100 qualified and suitable for automotive applications in environments up to 105 °C ambient temperature. LIN compliant drivers for the MSP430 MCU provided by IHR GmbH.
:
MSP430 devices are very popular in harsh environments such as industrial sensing for their low power consumption and innovative analog integration. Some harsh environment applications include transportation/automotive, renewable energy, military/space/avionics, mineral exploration, industrial, and safety & security.
Note that when the flash size is over 64K words, instruction addresses can no longer be encoded in just two bytes. This change in pointer size causes some incompatibilities with previous parts.

Peripherals

The MSP430 peripherals are generally easy to use, with consistent addresses between models, and no write-only registers.

General purpose I/O ports 0–10

If the peripheral is not needed, the pin may be used for general purpose I/O. The pins are divided into 8-bit groups called "ports", each of which is controlled by a number of 8-bit registers. In some cases, the ports are arranged in pairs which can be accessed as 16-bit registers.
The MSP430 family defines 11 I/O ports, P0 through P10, although no chip implements more than 10 of them. P0 is only implemented on the '3xx family. P7 through P10 are only implemented on the largest members of the '4xx and '2xx families. The newest '5xx and '6xx families has P1 through P11, and the control registers are reassigned to provide more port pairs.
Each port is controlled by the following registers. Ports which do not implement particular features do not implement the corresponding registers.
; PxIN : Port x input. This is a read-only register, and reflects the current state of the port's pins.
; PxOUT : Port x output. The values written to this read/write register are driven out the corresponding pins when they are configured to output.
; PxDIR : Port x data direction. Bits written as 1 configure the corresponding pin for output. Bits written as 0 configure the pin for input.
; PxSEL : Port x function select. Bits written as 1 configure the corresponding pin for use by the specialized peripheral. Bits written as 0 configure the pin for general purpose I/O. Port 0 is not multiplexed with other peripherals and does not have a P0SEL register.
; PxREN : Port x resistor enable. Bits set in this register enable weak pull-up or pull-down resistors on the corresponding I/O pins even when they are configured as inputs. The direction of the pull is set by the bit written to the PxOUT register.
; PxDS : Port x drive strength. Bits set in this register enable high current outputs. This increases output power, but may cause EMI.
Ports 0–2 can produce interrupts when inputs change. Additional registers configure this ability:
; PxIES : Port x interrupt edge select. Selects the edge which will cause the PxIFG bit to be set. When the input bit changes from matching the PxIES state to not matching it, the corresponding PxIFG bit is set.
; PxIE : Port x interrupt enable. When this bit and the corresponding PxIFG bit are both set, an interrupt is generated.
; PxIFG : Port x interrupt flag. Set whenever the corresponding pin makes the state change requested by PxIES. Can be cleared only by software.
; PxIV : Port x interrupt vector. This 16-bit register is a priority encoder which can be used to handle pin-change interrupts. If n is the lowest-numbered interrupt bit which is pending in PxIFG and enabled in PxIE, this register reads as 2n+2. If there is no such bit, it reads as 0. The scale factor of 2 allows direct use as an offset into a branch table. Reading this register also clears the reported PxIFG flag.
Some pins have special purposes either as inputs or outputs. In this case, the PxDIR bit controls which of the two functions the pin performs when the PxSEL bit is set. If there is only one special function, then PxDIR is generally ignored.
The PxIN register is still readable if the PxSEL bit is set, but interrupt generation is disabled. If PxSEL is clear, the special function's input is frozen and disconnected from the external pin. Also, configuring a pin for general purpose output does not disable interrupt generation.

Integrated peripherals

;Analog
;Timers
;System
;Communication and Interface
;Metering
;Display

Software development environment

Texas Instruments provides various hardware experimenter boards that support large and small MSP430 chips. TI also provides software development tools, both directly, and in conjunction with partners. One such toolchain is the IAR C/C++ compiler and Integrated development environment, or IDE. A Kickstart edition can be downloaded for free from TI or IAR; it is limited to 8 KB of C/C++ code in the compiler and debugger.
TI also combines a version of its own compiler and tools with its Eclipse-based Code Composer Studio IDE. It sells full-featured versions, and offers a free version for download which has a code size limit of 16 KB. CCS supports in-circuit emulators, and includes a simulator and other tools; it can also work with other processors sold by TI.
For those who are more comfortable with the Arduino, there is also another software Energia Energia, an open source electronics prototyping platform with the goal to bring the Wiring and Arduino framework to the Texas Instruments MSP430 based LaunchPad where Arduino code can be exported for programming MSP430 chips. The latest release of Energia supports the MSP-EXP430G2xxx, MSP-EXP430FR5739, MSP-EXP430FR5969, MSP-EXP430FR5994, MSP-EXP430F5529LP, Stellaris EK-LM4F120XL, Tiva-C EK-TM4C123GXL, Tiva-C EK-TM4C1294XL, CC3200 WiFi LaunchPad.
The open source community produces a freely available software development toolset based on the GNU toolset.
The GNU compiler is currently declined in three versions:
TI consulted with RedHat to provide official support for the MSP430 architecture to the GNU Compiler Collection C/C++ compiler. This is supported by TI's Code Composer Studio version 6.0 and higher.
There is a very early project, which may eventually provide better support for MSP430 in LLVM.
Other commercial development tool sets, which include editor, compiler, linker, assembler, debugger and in some cases code wizards, are available. VisSim, a block diagram language for model based development, generates efficient fixed point C-Code directly from the diagram. VisSim generated code for a closed loop ADC+PWM based PID control on the F2013 compiles to less than 1 KB flash and 100 bytes RAM. VisSim has on-chip peripheral blocks for the entire MSP430 family I²C, ADC, SD16, PWM.

Low cost development platforms

The MSP430F2013 and its siblings are set apart by the fact that it is the only MSP430 part that is available in a dual in-line package. Other variants in this family are only available in various surface-mount packages. TI has gone to some trouble to support the eZ430 development platform by making the raw chips easy for hobbyists to use in prototypes.

eZ430-F2013

TI has tackled the low-budget problem by offering a very small experimenter board, the eZ430-F2013, on a USB stick. This makes it easy for designers to choose the MSP430 chip for inexpensive development platforms that can be used with a computer. The eZ430-F2013 contains an MSP430F2013 microcontroller on a detachable prototyping board, and accompanying CD with development software. It is helpful for schools, hobbyists and garage inventors. It is also welcomed by engineers in large companies prototyping projects with capital budget problems.

MSP430 LaunchPad

released the MSP430 LaunchPad in July 2010. The MSP430 LaunchPad has an onboard flash emulator, USB, 2 programmable LEDs, and 1 programmable push button. As an addition to experimentation with the LaunchPad a is available.
TI has since provided several new LaunchPads based on the MSP430 platform:
All three of these LaunchPads include an eZ-FET JTAG debugger with backchannel UART capable of 1Mbit/s speeds. The FRAM LaunchPads include EnergyTrace, a feature supported by TI's Code Composer Studio IDE for monitoring and analyzing power consumption.

Debugging interface

In common with other microcontroller vendors, TI has developed a two-wire debugging interface found on some of their MSP430 parts that can replace the larger JTAG interface. The eZ430 Development Tool contains a full USB-connected flash emulation tool for this new two-wire protocol, named "Spy-Bi-Wire" by TI. Spy-Bi-Wire was initially introduced on only the smallest devices in the 'F2xx family with limited number of I/O pins, such as the MSP430F20xx, MSP430F21x2, and MSP430F22x2. The support for Spy-Bi-Wire has been expanded with the introduction of the latest '5xx family, where all devices have support Spy-Bi-Wire interface in addition to JTAG.
The advantage of the Spy-Bi-Wire protocol is that it uses only two communication lines, one of which is the dedicated _RESET line. The JTAG interface on the lower pin count MSP430 parts is multiplexed with general purpose I/O lines. This makes it relatively difficult to debug circuits built around the small, low-I/O-budget chips, since the full 4-pin JTAG hardware will conflict with anything else connected to those I/O lines. This problem is alleviated with the Spy-Bi-Wire-capable chips, which are still compatible with the normal JTAG interface for backwards compatibility with the old development tools.
JTAG debugging and flash programming tools based on OpenOCD and widely used in the ARM community are not available for the MSP430. Programming tools specially designed for the MSP430 are marginally less expensive than JTAG interfaces that use OpenOCD. However, should a project discover midstream that more MIPS, more memory, and more I/O peripherals are needed, those tools will not transfer to a processor from another vendor.

MSP430 CPU

The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers, of which four are dedicated to special purposes: R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a "constant generator" which reads as zero and ignores writes. Additional address mode encodings using R3 and R2 allow a total of six commonly used constant values without requiring an immediate operand word. R4 through R15 are available for general use.
The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in.B and.W suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to.W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field. Some special versions can be constructed using R0, and modes other than register direct using R2 and R3 are interpreted specially. Ad can use only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 or R1 are used with the autoincrement addressing mode, they are always incremented by two. Other registers are incremented by the operand size, either 1 or 2 bytes.
The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.

Pseudo-operations

A number of additional instructions are implemented as aliases for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as "MOV @SP+,PC". Emulated instructions are:
EmulatedActualDescription
ADC.x dstADDC.x #0,dstAdd carry to destination
BR dstMOV dst,PCBranch to destination
CLR.x dstMOV.x #0,dstClear destination
CLRCBIC #1,SRClear carry bit
CLRNBIC #4,SRClear negative bit
CLRZBIC #2,SRClear zero bit
DADC.x dstDADD.x #0,dstDecimal add carry to destination
DEC.x dstSUB.x #1,dstDecrement
DECD.x dstSUB.x #2,dstDouble decrement
DINTBIC #8,SRDisable interrupts
EINTBIS #8,SREnable interrupts
INC.x dstADD.x #1,dstIncrement
INCD.x dstADD.x #2,dstDouble increment
INV.x dstXOR.x #−1,dstInvert
NOPMOV #0,R3No operation
POP dstMOV @SP+,dstPop from stack
RETMOV @SP+,PCReturn from subroutine
RLA.x dstADD.x dst,dstRotate left arithmetic
RLC.x dstADDC.x dst,dstRotate left through carry
SBC.x dstSUBC.x #0,dstSubtract borrow from destination
SETCBIS #1,SRSet carry bit
SETNBIS #4,SRSet negative bit
SETZBIS #2,SRSet zero bit
TST.x dstCMP.x #0,dstTest destination

Note that the immediate constants −1, 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.

MSP430X 20-bit extension

The basic MSP430 cannot support more memory than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions:
  1. A limited number of 20-bit instructions for common operations, and
  2. A general prefix-word mechanism that can extend any instruction to 20 bits.
The extended instructions include some additional capabilities, notably multi-bit shifts and multi-register load/store operations.
20-bit operations use the length suffix "A" instead of.B or.W. .W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
All other instructions can have a prefix word added which extends them to 20 bits. The prefix word contains an additional operand size bit, which is combined with the existing B/W bit to specify the operand size. There is one unused size combination; there are indications that this might be used in future for a 32-bit operand size.
The prefix word comes in two formats, and the choice between them depends on the instruction which follows.
If the instruction has any non-register operands, then the simple form is used, which provides 2 4-bit fields to extend any offset or immediate constant in the instruction stream to 20 bits.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in, and a repeat count. A 4-bit field in the extension word encodes either a repeat count, or a register number which contains a 4-bit repeat count.

MSP430 address space

The general layout of the MSP430 address space is:
; 0x0000–0x0007 : Processor special function registers
; 0x0008–0x00FF : 8-bit peripherals. These must be accessed using 8-bit loads and stores.
; 0x0100–0x01FF : 16-bit peripherals. These must be accessed using 16-bit loads and stores.
; 0x0200–0x09FF : Up to 2048 bytes of RAM.
; 0x0C00–0x0FFF : 1024 bytes of bootstrap loader ROM.
; 0x1000–0x10FF : 256 bytes of data flash ROM.
; 0x1800-0x19FF : 512 bytes of data FRAM
; 0x1100–0x38FF : Extended RAM on models with more than 2048 bytes of RAM.
; 0x1100–0xFFFF : Up to 60 kilobytes of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vectors.
A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.
There is a new extended version of the architecture which allows a 20-bit address space. It allows additional program ROM beginning at 0x10000.
The '5xx series has a greatly redesigned address space, with the first 4K devoted to peripherals, and up to 16K of RAM.

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List of debugging tools (not complete)

NameManufacturerInterfaceProtocolStatus
MSP-FET430PIFParallel-PortJTAG-
MSP-FET430UIFUSB-InterfaceJTAG, Spy-Bi-Wire-
MSP-FETUSB-InterfaceJTAG, Spy-Bi-Wire-
MSP-430 LaunchPadUSB-InterfaceSpy-Bi-Wire-
MSP-430 LaunchPad eZ-FETUSB-InterfaceSpy-Bi-Wire-
eZ430-F2013USB-InterfaceSpy-Bi-Wire-
eZ430-RF2500USB-InterfaceSpy-Bi-Wire-
FETPParallel-PortJTAG-
USBPUSB-InterfaceJTAG, Spy-Bi-Wire
MSP430-JTAGParallel-PortJTAG-
MSP430-JTAG-ISOUSB-InterfaceJTAG, Spy-Bi-Wire
MSP430-JTAG-ISO-MK2USB-InterfaceJTAG, Spy-Bi-Wire-
MSP430-JTAG-TinyUSB-InterfaceJTAG, Spy-Bi-Wire
MSP430-JTAG-TINY-V2USB-InterfaceJTAG?, Spy-Bi-Wire-
MSP430-JTAG-RFUSB-InterfaceJTAG, Spy-Bi-Wire-
FlashPro-CCUSB-InterfaceJTAG, Spy-Bi-Wire, BSL-
VisSim/ECDUSB-InterfaceJTAG, Spy-Bi-Wire-
LA-3713USB-Interface / EthernetJTAG, Spy-bi-Wire-

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