Peripheral Component Interconnect

History

Auto configuration

Interrupts

Conventional hardware specifications

• clock with synchronous transfers
• Peak transfer rate of 133 MB/s for 32-bit bus width
• 32-bit bus width
• 32- or 64-bit memory address space
• 32-bit I/O port space
• 256-byte configuration space
• 5-volt signaling
• Reflected-wave switching

Card voltage and keying

Connector pinout

• Each slot has its own REQ# output to, and GNT# input from the motherboard arbiter.
• Each slot has its own IDSEL line, usually connected to a specific AD line.
• TDO is daisy-chained to the following slot's TDI. Cards without JTAG support must connect TDI to TDO so as not to break the chain.
• PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the motherboard. The motherboard may sense these pins to determine the presence of PCI cards and their power requirements.
• REQ64# and ACK64# are individually pulled up on 32-bit only slots.
• The interrupt lines INTA# through INTD# are connected to all slots in different orders.

• IOPWR is +3.3 V or +5 V, depending on the backplane. The slots also have a ridge in one of two places which prevents insertion of cards that do not have the corresponding key notch, indicating support for that voltage standard. Universal cards have both key notches and use IOPWR to determine their I/O signal levels.
• The PCI SIG strongly encourages 3.3 V PCI signaling, requiring support for it since standard revision 2.3, but most PC motherboards use the 5 V variant. Thus, while many currently available PCI cards support both, and have two key notches to indicate that, there are still a large number of 5 V-only cards on the market.
• The M66EN pin is an additional ground on 5 V PCI buses found in most PC motherboards. Cards and motherboards that do not support 66 MHz operation also ground this pin. If all participants support 66 MHz operation, a pull-up resistor on the motherboard raises this signal high and 66 MHz operation is enabled. The pin is still connected to ground via coupling capacitors on each card to preserve its AC shielding function.
• The PCIXCAP pin is an additional ground on PCI buses and cards. If all cards and the motherboard support the PCI-X protocol, a pull-up resistor on the motherboard raises this signal high and PCI-X operation is enabled. The pin is still connected to ground via coupling capacitors on each card to preserve its AC shielding function.
• At least one of PRSNT1# and PRSNT2# must be grounded by the card. The combination chosen indicates the total power requirements of the card.
• SBO# and SDONE are signals from a cache controller to the current target. They are not initiator outputs, but are colored that way because they are target inputs.
• PME# - Power management event which is supported in PCI and higher. It is a open drain, active low signal. PCI cards may use this signal to send and receive PME via the PCI socket directly, which eliminates the need for a special Wake-on-LAN cable.

  Mixing of 32-bit and 64-bit PCI cards in different width slots

Physical dimensions

• Standard: 120.02 mm;
• Low Profile: 79.20 mm.

• Short Card: 169.52;
• Long Card: 313.78.

• MD1: 121.79;
• MD2: 169.52;
• MD3: 243.18.

  Mini PCI

Technical details of Mini PCI

PCI bus transactions

PCI address spaces

PCI command codes

PCI bus latency

• A target must be able to complete the initial data phase within 16 cycles of the start of a transaction.
• An initiator must complete each data phase within 8 cycles.

Delayed transactions

PCI bus bridges

Posted writes

Combining, merging, and collapsing

PCI bus signals

Signal timing

Arbitration

Address phase

Address phase timing

 _ 0_ 1_ 2_ 3_ 4_ 5_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
 ___
 GNT# \___/XXXXXXXXXXXXXXXXXXX 
 _______
 FRAME# \___________________
 ___
 AD -------<___>--------------- 
 ___ _______________
 C/BE# -------<___X_______________ 
 _______________________
 DEVSEL# \___\___\___\___
 Fast Med Slow Subtractive
 _ _ _ _ _ _ _
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
 0 1 2 3 4 5

Dual-cycle address

 _ 0_ 1_ 2_ 3_ 4_ 5_ 6_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
 ___
 GNT# \___/XXXXXXXXXXXXXXXXXXXXXXX
 _______
 FRAME# \_______________________
 ___ ___
 AD -------<___X___>--------------- 
 ___ ___ _______________
 C/BE# -------<___X___X_______________ 
 ___________________________
 DEVSEL# \___\___\___\___
 Fast Med Slow
 _ _ _ _ _ _ _ _
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
 0 1 2 3 4 5 6

Configuration access

Data phases

 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
 ___ _______ ___ ___ ___
 AD ---<___XXXXXXXXX_______XXXXX___X___X___ 
 ___ ___ _______ ___ ___
 AD ---<___>~~~ ___ _______________ _______ ___ ___
 C/BE# ---<___X_______________X_______X___X___ 
 _______________ | ___ | | |
 IRDY# x \_______/ x \___________
 ___________________ | | | |
 TRDY# x x \___________________
 ___________ | | | |
 DEVSEL# \___________________________
 ___ | | | |
 FRAME# \___________________________________
 _ _ _ _ _ |_ _ |_ |_ |_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
 0 1 2 3 4 5 6 7 8 9

Fast DEVSEL# on reads

Ending transactions

Initiator burst termination

Target burst termination

Burst addressing

Transaction examples

 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 ___ ___ ___ ___ ___
 AD ---<___X___X___X___X___>---<___>
 ___ ___ ___ ___ ___
 C/BE# ---<___X___X___X___X___>---<___>
 | | | | ___
 IRDY# ^^^^^^^^\______________/ ^^^^^
 | | | | ___
 TRDY# ^^^^^^^^\______________/ ^^^^^
 | | | | ___
 DEVSEL# ^^^^^^^^\______________/ ^^^^^
 ___ | | | ___
 FRAME# \_______________/ | ^^^^\____
 _ _ |_ |_ |_ |_ _ _
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 0 1 2 3 4 5 6 7

 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 ___ ___ ___ ___ ___
 AD ---<___>---<___X___X___X___>---<___>
 ___ _______ ___ ___ ___
 C/BE# ---<___X_______X___X___X___>---<___>
 ___ | | | | ___
 IRDY# ^^^^\___________________/ ^^^^^
 ___ _____ | | | | ___
 TRDY# ^^^^ \______________/ ^^^^^
 ___ | | | | ___
 DEVSEL# ^^^^\___________________/ ^^^^^
 ___ | | | ___
 FRAME# \___________________/ | ^^^^\____
 _ _ _ |_ |_ |_ |_ _ _
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 0 1 2 3 4 5 6 7 8

 0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 ___ ___ ___ ___ ___
 AD ---<___>---<___X___X___X___XXXX>----
 ___ _______ ___ ___ ___ ___
 C/BE# ---<___X_______X___X___X___X___>----
 | | | | ___
 IRDY# ^^^^^^^\_______________________/
 _____ | | | | _______
 TRDY# ^^^^^^^ \______________/
 ________________ | ___
 STOP# ^^^^^^^ | | | \_______/
 | | | | ___
 DEVSEL# ^^^^^^^\_______________________/
 ___ | | | | ___
 FRAME# \_______________________/ ^^^^
 _ _ _ |_ |_ |_ |_ _ _
 CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
 0 1 2 3 4 5 6 7 8

Parity

Fast back-to-back transactions

• they are by the same initiator,
• the first transaction was a write, and
• the initiator still has permission to use the PCI bus.

• the current transaction was preceded by an idle cycle, or
• the previous transaction was to the same target, or
• the current transaction began with a double address cycle.

64-bit PCI

Cache snooping (obsolete)

Development tools