Multimedia Acceleration eXtensions


The Multimedia Acceleration eXtensions or MAX are instruction set extensions to the Hewlett-Packard PA-RISC instruction set architecture. MAX was developed to improve the performance of multimedia applications that were becoming more prevalent during the 1990s.
MAX instructions operate on 32- or 64-bit SIMD data types consisting of multiple 16-bit integers packed in general purpose registers. The available functionality includes additions, subtractions and shifts.
The first version, MAX-1, was for the 32-bit PA-RISC 1.1 ISA. The second version, MAX-2, was for the 64-bit PA-RISC 2.0 ISA.

Notability

The approach is notable because the set of instructions is much smaller than in other multimedia CPUs, and also more general-purpose. The small set and simplicity of the instructions reduce the recurring costs of the electronics, as well as the costs and difficulty of the design. The general-purpose nature of the instructions increases their overall value. These instructions require only small changes to a CPU's arithmetic-logic unit. A similar design approach promises to be a successful model for the multimedia instructions of other CPU designs. The set is also small because the CPU already included powerful shift and bit-manipulation instructions: "Shift pair" which shifts a pair of registers, "extract" and "insert" of bit fields, and all the common bit-wise logical operations.
This set of multimedia instructions has proven its performance, as well. In 1996 the 64-bit "MAX-2" instructions enabled real-time performance of MPEG-1 and MPEG-2 video while increasing the area of a RISC CPU by only 0.2%.

Implementations

MAX-1 was first implemented with the PA-7100LC in 1994. It is usually attributed as being the first SIMD extensions to an ISA. The second version, MAX-2, was for the 64-bit PA-RISC 2.0 ISA. It was first implemented in the PA-8000 microprocessor released in 1996.
The basic approach to the arithmetic in MAX-2 is to "interrupt the carries" between the 16-bit subwords, and choose between modular arithmetic, signed and unsigned saturation. This requires only small changes to the arithmetic logic unit.

MAX-1

MAX-2

MAX-2 instructions are register-to-register instructions that operate on multiple integers in 64-bit quantities. All have a one cycle latency in the PA-8000 microprocessor and its derivatives. Memory accesses are via the standard 64-bit loads and stores.
The "MIX" and "PERMH" instructions are a notable innovation because they permute words in the register set without accessing memory. This can substantially speed many operations.
InstructionDescription
HADDParallel add with modulo arithmetic
HADD,ssParallel add with signed saturation
HADD,usParallel add with unsigned saturation
HSUBParallel subtract with modulo arithmetic
HSUB,ssParallel subtract with signed saturation
HSUB,usParallel subtract with unsigned saturation
HSHLADDParallel shift left and add with signed saturation
HSHRADDParallel shift right and add with signed saturation
HAVGParallel average
HSHRParallel shift right signed
HSHR,uParallel shift right unsigned
HSHLParallel shift left
MIXMix 16-bit sub-words in a 64-bit word; MIX Left, Ra,Rb,Rc, Rc:=a1,b1,a3,b3; MIX Right, Rc:=a2,b2,a4,b4
MIXWMix 32-bit sub-words in a 64-bit word; e.g. MIXW Left, Ra,Rb,Rc, Rc:=a1,a2,b1,b2; MIXW Right, Rc:=a3,a4,b3,b4
PERMHPermute 16-bit sub-words of the source in any possible permutation in the destination register, including repetitions.