In the late 1970s, the industry had moved away from metal, as the gate material in the metal-oxide-semiconductor stack due to fabrication complications. A material called polysilicon was used to replace aluminum. Polysilicon can be deposited easily via chemical vapor deposition and is tolerant to subsequent manufacturing steps which involve extremely high temperatures, where metal was not. Particularly, metal has a tendency to disperse into silicon during these thermal annealing steps. In particular, when used on a silicon wafer with a < 1 1 1 > crystal orientation, excessive alloying of aluminum with the underlying silicon can create a short circuit between the diffused FET source or drain areas under the aluminum and across the metallurgical junction into the underlying substrate causing irreparable circuit failures. These shorts are created by pyramidal-shaped spikes of silicon-aluminum alloy pointing vertically "down" into the silicon wafer. The practical high-temperature limit for annealing aluminum on silicon is on the order of 450 °C. Polysilicon is also attractive for the easy manufacturing of self-aligned gates. The implantation or diffusion of source and drain dopant impurities is carried out with the gate in place, leading to a channel perfectly aligned to the gate without additional lithographic steps with the potential for misalignment of the layers.
In NMOS and CMOS technologies, over time and elevated temperatures, the positive voltages employed by the gate structure can cause any existing positively chargedsodium impurities directly under the positively charged gate to diffuse through the gate dielectric and migrate to the less-positively-charged channel surface, where the positive sodium charge has a higher effect on the channel creation thus lowering the threshold voltage of an N-channel transistor and potentially causing failures over time. Earlier PMOS technologies were not sensitive to this effect because the positively charged sodium was naturally attracted towards the negatively charged gate, and away from the channel, minimizing threshold voltage shifts. N-channel, metal gate processes imposed a very high standard of cleanliness difficult to achieve in that timeframe, resulting in high manufacturing costs. Polysilicon gates while sensitive to the same phenomenon, could be exposed to small amounts of HCl gas during subsequent high-temperature processing to react with any sodium, binding with it to form NaCl and carrying it away in the gas stream, leaving an essentially sodium-free gate structure greatly enhancing reliability. However, polysilicon doped at practical levels does not offer the near-zero electrical resistance of metals, and is therefore not ideal for charging and discharging the gate capacitance of the transistor resulting in slower circuitry. From the 45 nm node onward, the metal gate technology returns, together with the use of high-dielectric materials, pioneered by Intel developments. The candidates for the metal gate electrode are probably, for NMOS, Ta, TaN, Nb and for PMOS WN/RuO2. Due to this solution, the strain capacity on the channel can be improved. Moreover, this enables less current perturbations in the gate.
