MCST-R500S

MCST R500S Highlights

• implements the SPARC V8 instruction set architecture
• dual-core
• the two cores can work in redundancy to increase reliability of the system.
• core specifications:
• *in-order, single-issue
• *5-stage integer pipeline
• *7-stage floating-point pipeline
• *16 KB L1 instruction cache
• *32 KB L1 data cache
• shared 512KB L2 cache
• integrated controllers:
• *memory
• *PCI
• *RDMA
• *MSI
• *EBus
• *PS/2
• *Ethernet 100
• *SCSI-2
• *RS-232
• 500 МHz clock rate
• 130 nm process
• die size 100 mm²
• ~45 million transistors
• power consumption 5W