List of ARM microarchitectures
This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design. Keil also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.
ARM cores
Designed by ARM
As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads use with caution.Designed by third parties
These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.| Core Family | Instruction set | Microarchitecture | Feature | Cache, MMU | Typical MIPS @ MHz |
| StrongARM | ARMv4 | SA-110 | 5-stage pipeline | 16 KB / 16 KB, MMU | 100–233 MHz 1.0 DMIPS/MHz |
| StrongARM | ARMv4 | SA-1100 | derivative of the SA-110 | 16 KB / 8 KB, MMU | |
| Faraday | ARMv4 | FA510 | 6-stage pipeline | Up to 32 KB / 32 KB cache, MPU | 1.26 DMIPS/MHz 100–200 MHz |
| Faraday | ARMv4 | FA526 | 6-stage pipeline | Up to 32 KB / 32 KB cache, MMU | 1.26 MIPS/MHz 166–300 MHz |
| Faraday | ARMv4 | FA626 | 8-stage pipeline | 32 KB / 32 KB cache, MMU | 1.35 DMIPS/MHz 500 MHz |
| Faraday | ARMv5TE | FA606TE | 5-stage pipeline | No cache, no MMU | 1.22 DMIPS/MHz 200 MHz |
| Faraday | ARMv5TE | FA626TE | 8-stage pipeline | 32 KB / 32 KB cache, MMU | 1.43 MIPS/MHz 800 MHz |
| Faraday | ARMv5TE | FMP626TE | 8-stage pipeline, SMP | 32 KB / 32 KB cache, MMU | 1.43 MIPS/MHz 500 MHz |
| Faraday | ARMv5TE | FA726TE | 13 stage pipeline, dual issue | 32 KB / 32 KB cache, MMU | 2.4 DMIPS/MHz 1000 MHz |
| XScale | ARMv5TE | XScale | 7-stage pipeline, Thumb, enhanced DSP instructions | 32 KB / 32 KB, MMU | 133–400 MHz |
| XScale | ARMv5TE | Bulverde | Wireless MMX, wireless SpeedStep added | 32 KB / 32 KB, MMU | 312–624 MHz |
| XScale | ARMv5TE | Monahans | Wireless MMX2 added | 32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU | Up to 1.25 GHz |
| Sheeva | ARMv5 | Feroceon | 5–8 stage pipeline, single-issue | 16 KB / 16 KB, MMU | 600–2000 MHz |
| Sheeva | ARMv5 | Jolteon | 5–8 stage pipeline, dual-issue | 32 KB / 32 KB, MMU | 600–2000 MHz |
| Sheeva | ARMv5 | PJ1 | 5–8 stage pipeline, single-issue, Wireless MMX2 | 32 KB / 32 KB, MMU | 1.46 DMIPS/MHz 1.06 GHz |
| Sheeva | ARMv6 / ARMv7-A | PJ4 | 6–9 stage pipeline, dual-issue, Wireless MMX2, SMP | 32 KB / 32 KB, MMU | 2.41 DMIPS/MHz 1.6 GHz |
| Snapdragon | ARMv7-A | Scorpion | 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON | 256 KB L2 per core | 2.1 DMIPS/MHz per core |
| Snapdragon | ARMv7-A | Krait | 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON | 4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core | 3.3 DMIPS/MHz per core |
| Snapdragon | ARMv8-A | Kryo | 4 cores. | ? | Up to 2.2 GHz |
| Ax | ARMv7-A | Swift | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON | L1: 32 KB / 32 KB, L2: 1 MB | 3.5 DMIPS/MHz per core |
| Ax | ARMv8-A | Cyclone | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar. | L1: 64 KB / 64 KB, L2: 1 MB, L3: 4 MB | 1.3 or 1.4 GHz |
| Ax | ARMv8-A | Typhoon | 2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 | L1: 64 KB / 64 KB, L2: 1 MB or 2 MB, L3: 4 MB | 1.4 or 1.5 GHz |
| Ax | ARMv8-A | Twister | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 | L1: 64 KB / 64 KB, L2: 2 MB, L3: 4 MB or 0 MB | 1.85 or 2.26 GHz |
| Ax | ARMv8.1-A | Hurricane and Zephyr | Hurricane: 2 or 3 cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, out-of-order Zephyr: 2 or 3 cores. AArch64. | L1: 64 KB / 64 KB, L2: 3 MB or 8 MB, L3: 4 MB or 0 MB | 2.34 or 2.38 GHz |
| Ax | ARMv8.2-A | Monsoon and Mistral | Monsoon: 2 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift. | L1I: 128 KB, L1D: 64 KB, L2: 8 MB, L3: 4 MB | 2.39 GHz |
| Ax | ARMv8.3-A | Vortex and Tempest | Vortex: 2 or 4 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order Tempest: 4 cores. AArch64, 3-decode, out-of-order, superscalar. Based on Swift. | L1: 128 KB / 128 KB, L2: 8 MB, L3: 8 MB | 2.5 GHz |
| Ax | ARMv8.4-A | Lightning and Thunder | Lightning: 2 cores. AArch64, 7-decode, ?-issue, 11-wide, superscalar, out-of-order Thunder: 4 cores. AArch64, out-of-order, superscalar. | L1: 128 KB / 128 KB, L2: 8 MB, L3: 16 MB | 2.66 GHz |
| X-Gene | ARMv8-A | X-Gene | 64-bit, quad issue, SMP, 64 cores | Cache, MMU, virtualization | 3 GHz |
| Denver | ARMv8-A | Denver | 2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache, Denver1: 28nm, Denver2:16nm | 128 KB I-cache / 64 KB D-cache | Up to 2.5 GHz |
| Carmel | ARMv8 | Carmel | 2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache, functional safety, dual execution, parity & ECC | ? KB I-cache / ? KB D-cache | Up to ? GHz |
| ThunderX | ARMv8-A | ThunderX | 64-bit, with two models with 8–16 or 24–48 cores | ? | Up to 2.2 GHz |
| K12 | ARMv8-A | K12 | ? | ? | ? |
| Exynos | ARMv8-A | M1/M2 | 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order | 64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB | 5.1 DMIPS/MHz |
| Exynos | ARMv8-A | M3 | 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order | 64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB | ? |
| Exynos | ARMv8.2-A | M4 | 2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order | 64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB | ? |