Ling adder
In electronics, an adder is a combinatorial or sequential logic element which computes the n-bit sum of two numbers. The family of Ling adders is a particularly fast adder and is designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett Packard presented an innovative 64 bit adder in 0.5 μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4. See Naffzinger's paper below for more details.
