The LEON project was started by the European Space Agency in late 1997 to study and develop a high-performance processor to be used in European space projects. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a Single event upset tolerant sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient errors in combinational logic. The LEON family includes the first LEON1 VHSIC Hardware Description Language design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now part of Cobham, developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.
LEON processor models and distributions
A LEON processor can be implemented in programmable logic such as an FPGA or manufactured into an ASIC. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. All processors in the LEON series use the SPARC V8 RISC instruction set. LEON2 has a five-stage pipeline while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2 design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design. The standard LEON2 distribution includes the following support cores:
The LEON3, LEON3FT and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for FPGA development boards and for ASIC targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a plug and play extension to the on-chip AMBA bus. IP cores available in GRLIB also include:
Design Flow Documentation for the LEON into FPGA are available from the manufacturer and from third party resources.
Terminology
The term LEON2/LEON2-FT often refer to the LEON2 system-on-chip design, which is the LEON2 processor core together with the standard set of peripherals available in the LEON2 distribution. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. With LEON3 and LEON4 the name typically refers to only the processor core, while LEON/GRLIB is used to refer to the complete system-on-chip design.
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip designs. The full source code is available under the GNU GPL license, allowing use for any purpose without licensing fee. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications. There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes SMP support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline.
LEON3FT processor core
The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset errors in all on-chip RAM memories. The LEON3FT processor supports most of the functionality in the standard LEON3 processor, and adds the following features:
The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible. An FPGA implementation called LEON3FT-RTAX is proposed for critical space applications.
LEON4 processor core
In January 2010, the fourth version of the LEON processor was released. This release has the following new features:
