Freescale 683XX

• A fully static CPU core, capable of running at any clock speed from dead stop to maximum rated speed.
• A CPU core designed to minimize transistors while maximizing performance.
• A high-speed clocked serial interface for debugging called background debug mode. The 683xx-series was the first to have a clocked serial interface to the CPU to perform debugging. Now, many CPUs use a standard serial test interface, usually JTAG, for this purpose.
• The SIM, which eliminates much glue logic by providing chip selects and address decoding. The SIM also provides a clock generator, watchdogs for various system operations, configuration of processor pins, a periodic timer, and an interrupt controller.

• The Timing Processor Unit, which performs almost any timing related task: timers, counters, proportional pulse width control, pulse width measurement, pulse generation, stepper motor controllers, quadrature detection, etc. Freescale gives the development system and code away for free.
• An auxiliary random-access memory doubles as a programmable microcontroller store for the TPU.
• Some early models have two conventional counter-timers.
• A general purpose timer module provides pulse accumulators, capture/compare, and pulse-width modulation capabilities.
• Some models have a network interface processor in the form of a communication processor module and serial communications controllers which can be interfaced to Ethernet or HDLC busses.
• Most models have a queued serial module which provides both synchronous Serial Peripheral Interface, and logic-level RS232 UART capabilities.