COP8


The COP8 microcontroller from National Semiconductor is an 8-bit CISC core microcontroller, whose main features are:
It has a machine cycle of up to 2M cycles per second, but most versions seem to be overclockable to up to 2.8M cycles per second.

Registers and memory map

The COP8 uses separate instruction and data spaces. Instruction address space is 15-bit, while data addresses are 8-bit.
To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address.
The CPU has an 8-bit accumulator and 15-bit PC. 16 additional 8-bit registers and an 8-bit program status word are memory mapped. There are special instructions to access them, but general RAM access instructions may also be used.
The memory map is as follows:
AddressesUse
0x00–6FGeneral purpose RAM, used for stack
0x70–7FUnused, reads as all-ones to trap stack underflows
0x80–8FUnused, reads undefined
0x90–BFAdditional peripheral control registers
0xC0–CFPeripheral control registers.
0xD0–DFGeneral purpose I/O ports L, G, I, C and D
0xE0–E8Reserved
0xE9Microwire shift register
0xEA–EDTimer 1 registers
0xEECNTRL register, control bits for Microwire & Timer 1
0xEFPSW, CPU program status word.
0xF0–FBR0–R11, general purpose registers
0xFCR12, a.k.a. X, secondary indirect pointer register
0xFDR13, a.k.a. SP, stack pointer register
0xFER14, a.k.a. B, primary indirect pointer register
0xFFR15, a.k.a. S, data segment extension register

If RAM is not banked, then R15 is just another general-purpose register. If RAM is banked, then the low half of the data address space is directed to a RAM bank selected by S. The special purpose registers in the high half of the data address space are always visible. The data registers at 0xFx can be used to copy data between banks.
RAM banks other than bank 0 have all 128 bytes available. The stack is always on bank 0, no matter how the S register is set.

Control transfers

In addition to 3-byte JMP and JSR instructions which can address the entire address space, 2-byte versions of these instructions can jump within a 4K page. The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved.
There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved.
For short-distance branches, there are 63 1-byte instructions which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply.
Conditional branches are done using a number of conditional skip instructions. For example, IFEQ compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches.