Atmel AVR instruction set

Processor registers

Special purpose registers

• PC: 16- or 22-bit program counter
• SP: 8- or 16-bit stack pointer
• SREG: 8-bit status register
• RAMPX, RAMPY, RAMPZ, RAMPD and EIND: 8-bit segment registers that are prepended to 16-bit addresses in order to form 24-bit addresses; only available in parts with large address spaces.

  Status bits

0. C Carry flag. This is a borrow flag on subtracts. The INC and DEC instructions do not modify the carry flag, so they may be used to loop over multi-byte arithmetic operations.
1. Z Zero flag. Set to 1 when an arithmetic result is zero.
2. N Negative flag. Set to a copy of the most significant bit of an arithmetic result.
3. V Overflow flag. Set in case of two's complement overflow.
4. S Sign flag. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison.
5. H Half-carry flag. This is an internal carry from additions and is used to support BCD arithmetic.
6. T Bit copy. Special bit load and bit store instructions use this bit.
7. I Interrupt flag. Set when interrupts are enabled.

   Addressing

• The general purpose registers are addressed by their numbers, although the full 5-bit number is not stored in instructions that can only operate on a subset of those registers.
• I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable; some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as memory-mapped I/O in the data address space.
• The data address space maps the 32 general-purpose registers, all the I/O registers, and the RAM; it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively.
• Program memory has a separate address space, addressed as 16-bit words for the purpose of fetching instructions
• For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ.
• The EEPROM is memory-mapped in some devices; in others, it is not directly addressable and is instead accessed through address, data and control I/O registers.
• The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.

Instruction timing

Instruction list

• Rd and Rr are registers in the range R0–R31
• Rdh and Rrh are registers in the range R16–R31
• Rdq and Rrq are registers in the range R16–R23
• Rp is a register pair R25:R24, R27:R26, R29:R28 or R31:R30
• XYZ is a pointer register, either X or Y or Z
• YZ is a pointer register, either Y or Z
• s is a bit number in the status register
• b is a bit number in a general-purpose or I/O register
• K6 is a 6-bit immediate unsigned constant
• K8 is an 8-bit immediate constant; since it is used only in 8-bit operations, its signedness is irrelevant
• IO5 is a 5-bit I/O address covering the bit-addressable part of the I/O address space, i.e. the lower half
• IO6 is a 6-bit I/O address covering the full I/O address space
• D16 is a 16-bit data address covering 64 KiB; in parts with more than 64 KiB data space, the contents of the RAMPD segment register is prepended
• P22 is a 22-bit program address covering 2²² 16-bit words
• S7 and S12 are 7-bit signed displacements, in units of words, relative to the program address stored in the program counter

Instruction set inheritance

• core cpu features, added on more capable CPU cores
• memory addressing features, added on all models with memory large enough to require them
• optional features, a few peripherals that may or may not be present on a particular model.

Core CPU instructions

1. The "Classic" core has only the zero-operand form of the LPM instruction, which is equivalent to LPM r0,Z.
2. "Classic plus" adds the MOVW instruction for moving register pairs, and the more general form of the LPM instruction which permit an arbitrary destination register and auto-increment of the Z pointer.
3. "Enhanced" cores add the multiply instructions.
4. The XMEGA cores do not add new instructions per se, but make some significant changes:
5. * The memory map is reorganized, eliminating memory-mapping of the processor register file and expanding the I/O port range. Now the first 4K is special function registers, the second 4K is data flash, and normal RAM begins at 8K.
6. * It is not necessary to explicitly disable interrupts before adjusting the stack pointer registers ; any write to SPL automatically disables interrupts for 4 clock cycles to give time for SPH to be updated.
7. * Other multi-byte registers are provided with shadow registers to enable atomic read and write. When the lowest-order byte is read, the higher-order bytes are copied to the shadow registers, so reading them later produces a snapshot of the register at the time of the first read. Writes to low-order bytes are buffered until the highest-order byte is written, upon which the entire multi-byte register is updated atomically.
8. Later XMEGA cores add four atomic read-modify-write instructions: exchange, load-and-set, load-and-clear, and load-and-toggle. These help coordinate with direct memory access peripherals, notably a USB controller.

Memory addressing instructions

1. Models with >256 bytes of data address space have a 16-bit stack pointer, with the high half in the SPH register.
2. Models with >8 KiB of ROM add the 2-word JUMP and CALL instructions.
3. Models with >64 KiB of ROM add the ELPM instruction and corresponding RAMPZ register. LPM instructions zero-extend the ROM address in Z; ELPM instructions prepend the RAMPZ register for high bits. This is not the same thing as the more general LPM instruction; there exist "classic" models with only the zero-operand form of ELPM. When auto-increment is available, it updates the entire 24-bit address including RAMPZ.
4. models with >128 KiB of ROM have a 3-byte program counter. Subroutine calls and returns use an additional byte of stack space, there is a new EIND register to provide additional high bits for indirect jumps and calls, and there are new extended instructions EIJMP and EICALL which use EIND:Z as the destination address.
5. models with >64 KiB of RAM address space extend the 16-bit RAM addressing limits with RAMPX, RAMPY, RAMPZ and RAMPD registers. These provide additional high bits for addressing modes which use the X, Y, or Z register pairs, respectively, or the direct addressing instructions LDS/STS. Unlike ROM access, there are no distinct "extended" instructions; instead the RAMP registers are used unconditionally.

   Optional feature instructions

• SPM for storing to flash ROM, is present only on processors with flash ROM
• BREAK for invoking the on-chip debugger, is omitted on some small models without on-chip debugger support
• DES for performing Data Encryption Standard rounds, is present on XMEGA models with DES accelerator support

Instruction encoding

• = Source register
• = Source register
• = Source register
• RRRR = Source register pair
• = Destination register
• = Destination register
• = Destination register
• DDDD = Destination register pair
• pp = Register pair, W, X, Y or Z
• y = Y/Z register pair bit
• u = FMUL signed with 0=signed or 1=unsigned
• s = Store/load bit
• c = Call/jump
• cy = With carry
• e = Extend indirect jump/call address with EIND
• q = Extend program memory address with RAMPZ
• = I/O space address
• = I/O space address
• = Bit number
• B = Bit value
• = 4-bit unsigned constant
• = 6-bit unsigned constant
• = 8-bit constant