The AVR32 is a 32-bitRISC microcontroller architecture produced by Atmel. The microcontroller architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm and CPU architect Erik Renno in Atmel's Norwegian design center. Most instructions are executed in a single-cycle. The multiply–accumulate unit can perform a 32-bit × 16-bit + 48-bit arithmetic operation in two cycles, issued once per cycle. It does not resemble the 8-bit AVR microcontroller family, even though they were both designed at Atmel Norway, in Trondheim. Some of the debug-tools are similar. Support for AVR32 has been dropped from Linux as of kernel 4.12; Atmel has switched mostly to M variants of the ARM architecture.
Architecture
The AVR32 has at least two micro-architectures, the AVR32A and AVR32B. These differ in the instruction set architecture, register configurations and the use of caches for instructions and data. The AVR32A CPU cores are for inexpensive applications. They do not provide dedicated hardware registers for shadowing the register file, status and return address in interrupts. This saves chip area at the expense of slower interrupt-handling. The AVR32B CPU cores are designed for fast interrupts. They have dedicated registers to hold these values for interrupts, exceptions and supervisor calls. The AVR32B cores also support a Java virtual machine in hardware. The AVR32 instruction set has 16-bit and 32-bit instructions, similar to e.g. some ARM, with several specialized instructions not found in older ARMv5 or ARMv6 or MIPS32. Several U.S. patents are filed for the AVR32 ISA and design platform. Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for high code density and fast instructions with few clock cycles. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit code and ARMv5 32-bit code by as much as 50% on code-size and 3× on performance. Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claimed, at the time, used less power than any other 32-bit CPU. Then in March 2015, they claim their new Cortex-M0+-based microcontrollers, using ARM Holdings' ARM architecture, not their own instruction set, "has broken all ultra-low power performance barriers to date."
Implementations
The AVR32 architecture was used only in Atmel's own products. In 2006, Atmel launched the AVR32A: The AVR32 AP7 core, a 7-stage pipelined, cache-based design platform. This "AP7000" implements the AVR32B architecture, and supports SIMDDSP instructions to the RISC instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit and supports operating systems like Linux. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips. In 2007, Atmel launched the second AVR32: The AVR32 UC3 core. This is designed for microcontrollers, using on-chip flash memory for program storage and running without an MMU. The AVR32 UC3 core uses a three-stage pipelined Harvard architecture specially designed to optimize instruction fetches from on-chip flash memory. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. It shares more than 220 instructions with the AVR32B. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point DSP arithmetic. Both implementations can be combined with a compatible set of peripheral controllers and buses first seen in the AT91SAM ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products. Both AVR32 cores include a Nexus class 2+ based On-Chip Debug framework build with JTAG. The UC3 core, announced at the Electronica 2010 in Munich Germany on November 10, 2010, is the first 32-bit AVR microcontroller with an optional floating-point unit.
If the devicename ends in *AU this is an Audio version, these allow the execution of Atmel licensed Audio firmware IPs. If the devicename ends in *S it includes an AES Crypto Module. ;A0/A1 Series devices deliver 91 Dhrystone MIPS at 66 MHz and consume 40 mA @66 MHz at 3.3 V.
;A3/A4 Series devices deliver 91 Dhrystone MIPS at 66 MHz and consume 40 mA @66 MHz at 3.3 V.
;B Series deliver 72 Dhrystone MIPS at 60 MHz and consume 23 mA @66 MHz at 3.3V.
* ;C Series devices deliver 91 Dhrystone MIPS at 66 MHz and consume 40 mA @66 MHz at 3.3 V.
D Series The low-power UC3D embeds SleepWalking technology that allows a peripheral to wake the device from sleep mode.
;L Series deliver 64 Dhrystone MIPS at 50 MHz and consume 15 mA @50 MHz at 1.8 V.
